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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_mem_backbone.v] - Diff between revs 111 and 136

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//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
// Copyright (C) 2009 , Olivier Girard
//
//
// This source file may be used and distributed without restriction provided
// Redistribution and use in source and binary forms, with or without
// that this copyright statement is not removed from the file and that any
// modification, are permitted provided that the following conditions
// derivative work contains the original copyright notice and the associated
// are met:
// disclaimer.
//     * Redistributions of source code must retain the above copyright
//
//       notice, this list of conditions and the following disclaimer.
// This source file is free software; you can redistribute it and/or modify
//     * Redistributions in binary form must reproduce the above copyright
// it under the terms of the GNU Lesser General Public License as published
//       notice, this list of conditions and the following disclaimer in the
// by the Free Software Foundation; either version 2.1 of the License, or
//       documentation and/or other materials provided with the distribution.
// (at your option) any later version.
//     * Neither the name of the authors nor the names of its contributors
//
//       may be used to endorse or promote products derived from this software
// This source is distributed in the hope that it will be useful, but WITHOUT
//       without specific prior written permission.
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
//
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// License for more details.
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
//
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// You should have received a copy of the GNU Lesser General Public License
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// along with this source; if not, write to the Free Software Foundation,
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 
// THE POSSIBILITY OF SUCH DAMAGE
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//
//
// *File Name: omsp_mem_backbone.v
// *File Name: omsp_mem_backbone.v
// 
// 
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    fe_mab,                         // Frontend Memory address bus
    fe_mab,                         // Frontend Memory address bus
    fe_mb_en,                       // Frontend Memory bus enable
    fe_mb_en,                       // Frontend Memory bus enable
    mclk,                           // Main system clock
    mclk,                           // Main system clock
    per_dout,                       // Peripheral data output
    per_dout,                       // Peripheral data output
    pmem_dout,                      // Program Memory data output
    pmem_dout,                      // Program Memory data output
    puc_rst                         // Main system reset
    puc_rst,                        // Main system reset
 
    scan_enable                     // Scan enable (active during scan shifting)
);
);
 
 
// OUTPUTs
// OUTPUTs
//=========
//=========
output        [15:0] dbg_mem_din;   // Debug unit Memory data input
output        [15:0] dbg_mem_din;   // Debug unit Memory data input
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input                fe_mb_en;      // Frontend Memory bus enable
input                fe_mb_en;      // Frontend Memory bus enable
input                mclk;          // Main system clock
input                mclk;          // Main system clock
input         [15:0] per_dout;      // Peripheral data output
input         [15:0] per_dout;      // Peripheral data output
input         [15:0] pmem_dout;     // Program Memory data output
input         [15:0] pmem_dout;     // Program Memory data output
input                puc_rst;       // Main system reset
input                puc_rst;       // Main system reset
 
input                scan_enable;   // Scan enable (active during scan shifting)
 
 
 
 
//=============================================================================
//=============================================================================
// 1)  DECODER
// 1)  DECODER
//=============================================================================
//=============================================================================
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  else         fe_pmem_cen_dly <=  fe_pmem_cen;
  else         fe_pmem_cen_dly <=  fe_pmem_cen;
 
 
wire fe_pmem_save    = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st;
wire fe_pmem_save    = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st;
wire fe_pmem_restore = (~fe_pmem_cen &  fe_pmem_cen_dly) |  dbg_halt_st;
wire fe_pmem_restore = (~fe_pmem_cen &  fe_pmem_cen_dly) |  dbg_halt_st;
 
 
 
`ifdef CLOCK_GATING
 
wire mclk_bckup;
 
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup),
 
                                  .clk (mclk), .enable(fe_pmem_save), .scan_enable(scan_enable));
 
`else
 
wire mclk_bckup = mclk;
 
`endif
 
 
reg  [15:0] pmem_dout_bckup;
reg  [15:0] pmem_dout_bckup;
always @(posedge mclk or posedge puc_rst)
always @(posedge mclk_bckup or posedge puc_rst)
  if (puc_rst)           pmem_dout_bckup     <=  16'h0000;
  if (puc_rst)           pmem_dout_bckup     <=  16'h0000;
 
`ifdef CLOCK_GATING
 
  else                   pmem_dout_bckup     <=  pmem_dout;
 
`else
  else if (fe_pmem_save) pmem_dout_bckup     <=  pmem_dout;
  else if (fe_pmem_save) pmem_dout_bckup     <=  pmem_dout;
 
`endif
 
 
// Mux between the ROM data and the backup
// Mux between the ROM data and the backup
reg         pmem_dout_bckup_sel;
reg         pmem_dout_bckup_sel;
always @(posedge mclk or posedge puc_rst)
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)              pmem_dout_bckup_sel <=  1'b0;
  if (puc_rst)              pmem_dout_bckup_sel <=  1'b0;

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