URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 136 |
Rev 151 |
Line 34... |
Line 34... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 103 $
|
// $Rev: 134 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
|
// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_defines.v"
|
`include "openMSP430_defines.v"
|
`endif
|
`endif
|
Line 177... |
Line 177... |
wire fe_pmem_wait = (~fe_pmem_cen & ~eu_pmem_cen);
|
wire fe_pmem_wait = (~fe_pmem_cen & ~eu_pmem_cen);
|
|
|
|
|
// Peripherals
|
// Peripherals
|
//--------------------
|
//--------------------
|
wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:`PER_AWIDTH+1]=={15-`PER_AWIDTH{1'b0}});
|
wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:1]<(`PER_SIZE>>1));
|
wire eu_per_en = eu_mb_en & (eu_mab[14:`PER_AWIDTH] =={15-`PER_AWIDTH{1'b0}});
|
wire eu_per_en = eu_mb_en & (eu_mab<(`PER_SIZE>>1));
|
|
|
wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out;
|
wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out;
|
wire [1:0] per_we = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
|
wire [1:0] per_we = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
|
wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en;
|
wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en;
|
wire [`PER_MSB:0] per_addr_mux = dbg_mem_en ? dbg_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0];
|
wire [`PER_MSB:0] per_addr_mux = dbg_mem_en ? dbg_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0];
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.