| Line 49... |
Line 49... |
// INPUTs
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// INPUTs
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mclk, // Main system clock
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mclk, // Main system clock
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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per_wen, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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puc // Main system reset
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puc // Main system reset
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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| Line 63... |
Line 63... |
//=========
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//=========
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input mclk; // Main system clock
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input mclk; // Main system clock
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input [7:0] per_addr; // Peripheral address
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input [7:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input per_en; // Peripheral enable (high active)
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input [1:0] per_wen; // Peripheral write enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input puc; // Main system reset
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input puc; // Main system reset
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//=============================================================================
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//=============================================================================
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// 1) PARAMETER/REGISTERS & WIRE DECLARATION
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// 1) PARAMETER/REGISTERS & WIRE DECLARATION
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| Line 119... |
Line 119... |
SUMEXT : reg_dec = SUMEXT_D;
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SUMEXT : reg_dec = SUMEXT_D;
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default : reg_dec = {512{1'b0}};
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default : reg_dec = {512{1'b0}};
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endcase
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endcase
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// Read/Write probes
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// Read/Write probes
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wire reg_write = |per_wen & per_en;
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wire reg_write = |per_we & per_en;
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wire reg_read = ~|per_wen & per_en;
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wire reg_read = ~|per_we & per_en;
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// Read/Write vectors
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// Read/Write vectors
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wire [511:0] reg_wr = reg_dec & {512{reg_write}};
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wire [511:0] reg_wr = reg_dec & {512{reg_write}};
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wire [511:0] reg_rd = reg_dec & {512{reg_read}};
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wire [511:0] reg_rd = reg_dec & {512{reg_read}};
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