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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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// Copyright (C) 2009 , Olivier Girard
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// Redistribution and use in source and binary forms, with or without
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// modification, are permitted provided that the following conditions
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// are met:
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// License for more details.
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the authors nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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//
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// You should have received a copy of the GNU Lesser General Public License
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// along with this source; if not, write to the Free Software Foundation,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: omsp_multiplier.v
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// *File Name: omsp_multiplier.v
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//
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//
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mclk, // Main system clock
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mclk, // Main system clock
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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per_we, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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puc_rst // Main system reset
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puc_rst, // Main system reset
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scan_enable // Scan enable (active during scan shifting)
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output [15:0] per_dout; // Peripheral data output
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output [15:0] per_dout; // Peripheral data output
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input [13:0] per_addr; // Peripheral address
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input [13:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input per_en; // Peripheral enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input puc_rst; // Main system reset
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input puc_rst; // Main system reset
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input scan_enable; // Scan enable (active during scan shifting)
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//=============================================================================
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//=============================================================================
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// 1) PARAMETER/REGISTERS & WIRE DECLARATION
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// 1) PARAMETER/REGISTERS & WIRE DECLARATION
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//=============================================================================
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//=============================================================================
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RESLO = 'hA,
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RESLO = 'hA,
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RESHI = 'hC,
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RESHI = 'hC,
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SUMEXT = 'hE;
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SUMEXT = 'hE;
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// Register one-hot decoder utilities
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// Register one-hot decoder utilities
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parameter DEC_SZ = 2**DEC_WD;
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parameter DEC_SZ = (1 << DEC_WD);
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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// Register one-hot decoder
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// Register one-hot decoder
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parameter [DEC_SZ-1:0] OP1_MPY_D = (BASE_REG << OP1_MPY),
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parameter [DEC_SZ-1:0] OP1_MPY_D = (BASE_REG << OP1_MPY),
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OP1_MPYS_D = (BASE_REG << OP1_MPYS),
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OP1_MPYS_D = (BASE_REG << OP1_MPYS),
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wire op1_wr = reg_wr[OP1_MPY] |
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wire op1_wr = reg_wr[OP1_MPY] |
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reg_wr[OP1_MPYS] |
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reg_wr[OP1_MPYS] |
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reg_wr[OP1_MAC] |
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reg_wr[OP1_MAC] |
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reg_wr[OP1_MACS];
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reg_wr[OP1_MACS];
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always @ (posedge mclk or posedge puc_rst)
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`ifdef CLOCK_GATING
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wire mclk_op1;
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omsp_clock_gate clock_gate_op1 (.gclk(mclk_op1),
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.clk (mclk), .enable(op1_wr), .scan_enable(scan_enable));
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`else
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wire mclk_op1 = mclk;
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`endif
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always @ (posedge mclk_op1 or posedge puc_rst)
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if (puc_rst) op1 <= 16'h0000;
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if (puc_rst) op1 <= 16'h0000;
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`ifdef CLOCK_GATING
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else op1 <= per_din;
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`else
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else if (op1_wr) op1 <= per_din;
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else if (op1_wr) op1 <= per_din;
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`endif
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wire [15:0] op1_rd = op1;
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wire [15:0] op1_rd = op1;
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// OP2 Register
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// OP2 Register
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//-----------------
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//-----------------
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reg [15:0] op2;
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reg [15:0] op2;
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wire op2_wr = reg_wr[OP2];
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wire op2_wr = reg_wr[OP2];
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always @ (posedge mclk or posedge puc_rst)
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`ifdef CLOCK_GATING
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wire mclk_op2;
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omsp_clock_gate clock_gate_op2 (.gclk(mclk_op2),
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.clk (mclk), .enable(op2_wr), .scan_enable(scan_enable));
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`else
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wire mclk_op2 = mclk;
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`endif
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always @ (posedge mclk_op2 or posedge puc_rst)
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if (puc_rst) op2 <= 16'h0000;
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if (puc_rst) op2 <= 16'h0000;
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`ifdef CLOCK_GATING
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else op2 <= per_din;
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`else
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else if (op2_wr) op2 <= per_din;
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else if (op2_wr) op2 <= per_din;
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`endif
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wire [15:0] op2_rd = op2;
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wire [15:0] op2_rd = op2;
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// RESLO Register
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// RESLO Register
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reg [15:0] reslo;
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reg [15:0] reslo;
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wire [15:0] reslo_nxt;
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wire [15:0] reslo_nxt;
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wire reslo_wr = reg_wr[RESLO];
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wire reslo_wr = reg_wr[RESLO];
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always @ (posedge mclk or posedge puc_rst)
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`ifdef CLOCK_GATING
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wire reslo_en = reslo_wr | result_clr | result_wr;
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wire mclk_reslo;
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omsp_clock_gate clock_gate_reslo (.gclk(mclk_reslo),
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.clk (mclk), .enable(reslo_en), .scan_enable(scan_enable));
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`else
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wire mclk_reslo = mclk;
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`endif
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always @ (posedge mclk_reslo or posedge puc_rst)
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if (puc_rst) reslo <= 16'h0000;
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if (puc_rst) reslo <= 16'h0000;
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else if (reslo_wr) reslo <= per_din;
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else if (reslo_wr) reslo <= per_din;
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else if (result_clr) reslo <= 16'h0000;
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else if (result_clr) reslo <= 16'h0000;
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`ifdef CLOCK_GATING
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else reslo <= reslo_nxt;
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`else
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else if (result_wr) reslo <= reslo_nxt;
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else if (result_wr) reslo <= reslo_nxt;
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`endif
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wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo;
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wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo;
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// RESHI Register
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// RESHI Register
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Line 236... |
reg [15:0] reshi;
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reg [15:0] reshi;
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wire [15:0] reshi_nxt;
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wire [15:0] reshi_nxt;
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wire reshi_wr = reg_wr[RESHI];
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wire reshi_wr = reg_wr[RESHI];
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always @ (posedge mclk or posedge puc_rst)
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`ifdef CLOCK_GATING
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wire reshi_en = reshi_wr | result_clr | result_wr;
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wire mclk_reshi;
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omsp_clock_gate clock_gate_reshi (.gclk(mclk_reshi),
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.clk (mclk), .enable(reshi_en), .scan_enable(scan_enable));
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`else
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wire mclk_reshi = mclk;
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`endif
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always @ (posedge mclk_reshi or posedge puc_rst)
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if (puc_rst) reshi <= 16'h0000;
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if (puc_rst) reshi <= 16'h0000;
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else if (reshi_wr) reshi <= per_din;
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else if (reshi_wr) reshi <= per_din;
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else if (result_clr) reshi <= 16'h0000;
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else if (result_clr) reshi <= 16'h0000;
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`ifdef CLOCK_GATING
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else reshi <= reshi_nxt;
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`else
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else if (result_wr) reshi <= reshi_nxt;
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else if (result_wr) reshi <= reshi_nxt;
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`endif
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wire [15:0] reshi_rd = early_read ? reshi_nxt : reshi;
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wire [15:0] reshi_rd = early_read ? reshi_nxt : reshi;
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// SUMEXT Register
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// SUMEXT Register
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// Multiplier configuration
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// Multiplier configuration
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//--------------------------
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//--------------------------
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// Detect signed mode
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// Detect signed mode
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reg sign_sel;
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reg sign_sel;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk_op1 or posedge puc_rst)
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if (puc_rst) sign_sel <= 1'b0;
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if (puc_rst) sign_sel <= 1'b0;
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`ifdef CLOCK_GATING
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else sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
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`else
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else if (op1_wr) sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
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else if (op1_wr) sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
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`endif
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// Detect accumulate mode
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// Detect accumulate mode
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reg acc_sel;
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reg acc_sel;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk_op1 or posedge puc_rst)
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if (puc_rst) acc_sel <= 1'b0;
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if (puc_rst) acc_sel <= 1'b0;
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`ifdef CLOCK_GATING
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else acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS];
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`else
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else if (op1_wr) acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS];
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else if (op1_wr) acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS];
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`endif
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// Detect whenever the RESHI and RESLO registers should be cleared
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// Detect whenever the RESHI and RESLO registers should be cleared
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assign result_clr = op2_wr & ~acc_sel;
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assign result_clr = op2_wr & ~acc_sel;
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