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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_multiplier.v] - Diff between revs 111 and 136

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Line 1... Line 1...
 
 
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
// Copyright (C) 2009 , Olivier Girard
//
 
// This source file may be used and distributed without restriction provided
 
// that this copyright statement is not removed from the file and that any
 
// derivative work contains the original copyright notice and the associated
 
// disclaimer.
 
//
 
// This source file is free software; you can redistribute it and/or modify
 
// it under the terms of the GNU Lesser General Public License as published
 
// by the Free Software Foundation; either version 2.1 of the License, or
 
// (at your option) any later version.
 
//
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// Redistribution and use in source and binary forms, with or without
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// modification, are permitted provided that the following conditions
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// are met:
// License for more details.
//     * Redistributions of source code must retain the above copyright
 
//       notice, this list of conditions and the following disclaimer.
 
//     * Redistributions in binary form must reproduce the above copyright
 
//       notice, this list of conditions and the following disclaimer in the
 
//       documentation and/or other materials provided with the distribution.
 
//     * Neither the name of the authors nor the names of its contributors
 
//       may be used to endorse or promote products derived from this software
 
//       without specific prior written permission.
//
//
// You should have received a copy of the GNU Lesser General Public License
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// along with this source; if not, write to the Free Software Foundation,
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
 
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 
// THE POSSIBILITY OF SUCH DAMAGE
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//
//
// *File Name: omsp_multiplier.v
// *File Name: omsp_multiplier.v
// 
// 
Line 50... Line 54...
    mclk,                           // Main system clock
    mclk,                           // Main system clock
    per_addr,                       // Peripheral address
    per_addr,                       // Peripheral address
    per_din,                        // Peripheral data input
    per_din,                        // Peripheral data input
    per_en,                         // Peripheral enable (high active)
    per_en,                         // Peripheral enable (high active)
    per_we,                         // Peripheral write enable (high active)
    per_we,                         // Peripheral write enable (high active)
    puc_rst                         // Main system reset
    puc_rst,                        // Main system reset
 
    scan_enable                     // Scan enable (active during scan shifting)
);
);
 
 
// OUTPUTs
// OUTPUTs
//=========
//=========
output       [15:0] per_dout;       // Peripheral data output
output       [15:0] per_dout;       // Peripheral data output
Line 65... Line 70...
input        [13:0] per_addr;       // Peripheral address
input        [13:0] per_addr;       // Peripheral address
input        [15:0] per_din;        // Peripheral data input
input        [15:0] per_din;        // Peripheral data input
input               per_en;         // Peripheral enable (high active)
input               per_en;         // Peripheral enable (high active)
input         [1:0] per_we;         // Peripheral write enable (high active)
input         [1:0] per_we;         // Peripheral write enable (high active)
input               puc_rst;        // Main system reset
input               puc_rst;        // Main system reset
 
input               scan_enable;    // Scan enable (active during scan shifting)
 
 
 
 
//=============================================================================
//=============================================================================
// 1)  PARAMETER/REGISTERS & WIRE DECLARATION
// 1)  PARAMETER/REGISTERS & WIRE DECLARATION
//=============================================================================
//=============================================================================
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                       RESLO       = 'hA,
                       RESLO       = 'hA,
                       RESHI       = 'hC,
                       RESHI       = 'hC,
                       SUMEXT      = 'hE;
                       SUMEXT      = 'hE;
 
 
// Register one-hot decoder utilities
// Register one-hot decoder utilities
parameter              DEC_SZ      =  2**DEC_WD;
parameter              DEC_SZ      =  (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
 
 
// Register one-hot decoder
// Register one-hot decoder
parameter [DEC_SZ-1:0] OP1_MPY_D   = (BASE_REG << OP1_MPY),
parameter [DEC_SZ-1:0] OP1_MPY_D   = (BASE_REG << OP1_MPY),
                       OP1_MPYS_D  = (BASE_REG << OP1_MPYS),
                       OP1_MPYS_D  = (BASE_REG << OP1_MPYS),
Line 150... Line 156...
wire        op1_wr = reg_wr[OP1_MPY]  |
wire        op1_wr = reg_wr[OP1_MPY]  |
                     reg_wr[OP1_MPYS] |
                     reg_wr[OP1_MPYS] |
                     reg_wr[OP1_MAC]  |
                     reg_wr[OP1_MAC]  |
                     reg_wr[OP1_MACS];
                     reg_wr[OP1_MACS];
 
 
always @ (posedge mclk or posedge puc_rst)
`ifdef CLOCK_GATING
 
wire        mclk_op1;
 
omsp_clock_gate clock_gate_op1 (.gclk(mclk_op1),
 
                                .clk (mclk), .enable(op1_wr), .scan_enable(scan_enable));
 
`else
 
wire        mclk_op1 = mclk;
 
`endif
 
 
 
always @ (posedge mclk_op1 or posedge puc_rst)
  if (puc_rst)      op1 <=  16'h0000;
  if (puc_rst)      op1 <=  16'h0000;
 
`ifdef CLOCK_GATING
 
  else              op1 <=  per_din;
 
`else
  else if (op1_wr)  op1 <=  per_din;
  else if (op1_wr)  op1 <=  per_din;
 
`endif
 
 
wire [15:0] op1_rd  = op1;
wire [15:0] op1_rd  = op1;
 
 
 
 
// OP2 Register
// OP2 Register
//-----------------   
//-----------------   
reg  [15:0] op2;
reg  [15:0] op2;
 
 
wire        op2_wr = reg_wr[OP2];
wire        op2_wr = reg_wr[OP2];
 
 
always @ (posedge mclk or posedge puc_rst)
`ifdef CLOCK_GATING
 
wire        mclk_op2;
 
omsp_clock_gate clock_gate_op2 (.gclk(mclk_op2),
 
                                .clk (mclk), .enable(op2_wr), .scan_enable(scan_enable));
 
`else
 
wire        mclk_op2 = mclk;
 
`endif
 
 
 
always @ (posedge mclk_op2 or posedge puc_rst)
  if (puc_rst)      op2 <=  16'h0000;
  if (puc_rst)      op2 <=  16'h0000;
 
`ifdef CLOCK_GATING
 
  else              op2 <=  per_din;
 
`else
  else if (op2_wr)  op2 <=  per_din;
  else if (op2_wr)  op2 <=  per_din;
 
`endif
 
 
wire [15:0] op2_rd  = op2;
wire [15:0] op2_rd  = op2;
 
 
 
 
// RESLO Register
// RESLO Register
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reg  [15:0] reslo;
reg  [15:0] reslo;
 
 
wire [15:0] reslo_nxt;
wire [15:0] reslo_nxt;
wire        reslo_wr = reg_wr[RESLO];
wire        reslo_wr = reg_wr[RESLO];
 
 
always @ (posedge mclk or posedge puc_rst)
`ifdef CLOCK_GATING
 
wire        reslo_en = reslo_wr | result_clr | result_wr;
 
wire        mclk_reslo;
 
omsp_clock_gate clock_gate_reslo (.gclk(mclk_reslo),
 
                                  .clk (mclk), .enable(reslo_en), .scan_enable(scan_enable));
 
`else
 
wire        mclk_reslo = mclk;
 
`endif
 
 
 
always @ (posedge mclk_reslo or posedge puc_rst)
  if (puc_rst)         reslo <=  16'h0000;
  if (puc_rst)         reslo <=  16'h0000;
  else if (reslo_wr)   reslo <=  per_din;
  else if (reslo_wr)   reslo <=  per_din;
  else if (result_clr) reslo <=  16'h0000;
  else if (result_clr) reslo <=  16'h0000;
 
`ifdef CLOCK_GATING
 
  else                 reslo <=  reslo_nxt;
 
`else
  else if (result_wr)  reslo <=  reslo_nxt;
  else if (result_wr)  reslo <=  reslo_nxt;
 
`endif
 
 
wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo;
wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo;
 
 
 
 
// RESHI Register
// RESHI Register
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reg  [15:0] reshi;
reg  [15:0] reshi;
 
 
wire [15:0] reshi_nxt;
wire [15:0] reshi_nxt;
wire        reshi_wr = reg_wr[RESHI];
wire        reshi_wr = reg_wr[RESHI];
 
 
always @ (posedge mclk or posedge puc_rst)
`ifdef CLOCK_GATING
 
wire        reshi_en = reshi_wr | result_clr | result_wr;
 
wire        mclk_reshi;
 
omsp_clock_gate clock_gate_reshi (.gclk(mclk_reshi),
 
                                  .clk (mclk), .enable(reshi_en), .scan_enable(scan_enable));
 
`else
 
wire        mclk_reshi = mclk;
 
`endif
 
 
 
always @ (posedge mclk_reshi or posedge puc_rst)
  if (puc_rst)         reshi <=  16'h0000;
  if (puc_rst)         reshi <=  16'h0000;
  else if (reshi_wr)   reshi <=  per_din;
  else if (reshi_wr)   reshi <=  per_din;
  else if (result_clr) reshi <=  16'h0000;
  else if (result_clr) reshi <=  16'h0000;
 
`ifdef CLOCK_GATING
 
  else                 reshi <=  reshi_nxt;
 
`else
  else if (result_wr)  reshi <=  reshi_nxt;
  else if (result_wr)  reshi <=  reshi_nxt;
 
`endif
 
 
wire [15:0] reshi_rd = early_read ? reshi_nxt  : reshi;
wire [15:0] reshi_rd = early_read ? reshi_nxt  : reshi;
 
 
 
 
// SUMEXT Register
// SUMEXT Register
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// Multiplier configuration
// Multiplier configuration
//--------------------------
//--------------------------
 
 
// Detect signed mode
// Detect signed mode
reg sign_sel;
reg sign_sel;
always @ (posedge mclk or posedge puc_rst)
always @ (posedge mclk_op1 or posedge puc_rst)
  if (puc_rst)     sign_sel <=  1'b0;
  if (puc_rst)     sign_sel <=  1'b0;
 
`ifdef CLOCK_GATING
 
  else             sign_sel <=  reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
 
`else
  else if (op1_wr) sign_sel <=  reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
  else if (op1_wr) sign_sel <=  reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
 
`endif
 
 
 
 
// Detect accumulate mode
// Detect accumulate mode
reg acc_sel;
reg acc_sel;
always @ (posedge mclk or posedge puc_rst)
always @ (posedge mclk_op1 or posedge puc_rst)
  if (puc_rst)     acc_sel  <=  1'b0;
  if (puc_rst)     acc_sel  <=  1'b0;
 
`ifdef CLOCK_GATING
 
  else             acc_sel  <=  reg_wr[OP1_MAC]  | reg_wr[OP1_MACS];
 
`else
  else if (op1_wr) acc_sel  <=  reg_wr[OP1_MAC]  | reg_wr[OP1_MACS];
  else if (op1_wr) acc_sel  <=  reg_wr[OP1_MAC]  | reg_wr[OP1_MACS];
 
`endif
 
 
 
 
// Detect whenever the RESHI and RESLO registers should be cleared
// Detect whenever the RESHI and RESLO registers should be cleared
assign      result_clr = op2_wr & ~acc_sel;
assign      result_clr = op2_wr & ~acc_sel;
 
 

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