URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_multiplier.v] - Diff between revs 186 and 202

Rev 186	Rev 202
Line 163...	Line 163...
`ifdef CLOCK_GATING	`ifdef CLOCK_GATING
`wire mclk_op1;`	`wire mclk_op1;`
`omsp_clock_gate clock_gate_op1 (.gclk(mclk_op1),`	`omsp_clock_gate clock_gate_op1 (.gclk(mclk_op1),`
`.clk (mclk), .enable(op1_wr), .scan_enable(scan_enable));`	`.clk (mclk), .enable(op1_wr), .scan_enable(scan_enable));`
`else	`else
	`wire UNUSED_scan_enable = scan_enable;`
`wire mclk_op1 = mclk;`	`wire mclk_op1 = mclk;`
`endif	`endif

`always @ (posedge mclk_op1 or posedge puc_rst)`	`always @ (posedge mclk_op1 or posedge puc_rst)`
`if (puc_rst) op1 <= 16'h0000;`	`if (puc_rst) op1 <= 16'h0000;`