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Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 106 $
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// $Rev: 103 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 55... |
Line 55... |
per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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per_we, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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por, // Power-on reset
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por, // Power-on reset
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puc, // Main system reset
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puc_rst, // Main system reset
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wdtifg_clr, // Clear Watchdog-timer interrupt flag
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wdtifg_clr, // Clear Watchdog-timer interrupt flag
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wdtifg_set, // Set Watchdog-timer interrupt flag
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wdtifg_set, // Set Watchdog-timer interrupt flag
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wdtpw_error, // Watchdog-timer password error
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wdtpw_error, // Watchdog-timer password error
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wdttmsel // Watchdog-timer mode select
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wdttmsel // Watchdog-timer mode select
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);
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);
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Line 74... |
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// INPUTs
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// INPUTs
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//=========
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//=========
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input mclk; // Main system clock
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input mclk; // Main system clock
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input nmi_acc; // Non-Maskable interrupt request accepted
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input nmi_acc; // Non-Maskable interrupt request accepted
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input [7:0] per_addr; // Peripheral address
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input [13:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input per_en; // Peripheral enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input por; // Power-on reset
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input por; // Power-on reset
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input puc; // Main system reset
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input puc_rst; // Main system reset
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input wdtifg_clr; // Clear Watchdog-timer interrupt flag
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input wdtifg_clr; // Clear Watchdog-timer interrupt flag
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input wdtifg_set; // Set Watchdog-timer interrupt flag
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input wdtifg_set; // Set Watchdog-timer interrupt flag
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input wdtpw_error; // Watchdog-timer password error
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input wdtpw_error; // Watchdog-timer password error
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input wdttmsel; // Watchdog-timer mode select
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input wdttmsel; // Watchdog-timer mode select
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//=============================================================================
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//=============================================================================
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// 1) PARAMETER DECLARATION
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// 1) PARAMETER DECLARATION
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//=============================================================================
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//=============================================================================
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// Register addresses
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// Register base address (must be aligned to decoder bit width)
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parameter IE1 = 9'h000;
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parameter [14:0] BASE_ADDR = 15'h0000;
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parameter IFG1 = 9'h002;
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// Decoder bit width (defines how many bits are considered for address decoding)
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parameter DEC_WD = 2;
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// Register addresses offset
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parameter [DEC_WD-1:0] IE1 = 'h0,
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IFG1 = 'h2;
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// Register one-hot decoder utilities
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parameter DEC_SZ = 2**DEC_WD;
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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// Register one-hot decoder
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// Register one-hot decoder
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parameter IE1_D = (256'h1 << (IE1 /2));
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parameter [DEC_SZ-1:0] IE1_D = (BASE_REG << IE1),
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parameter IFG1_D = (256'h1 << (IFG1 /2));
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IFG1_D = (BASE_REG << IFG1);
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//============================================================================
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//============================================================================
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// 2) REGISTER DECODER
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// 2) REGISTER DECODER
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//============================================================================
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//============================================================================
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// Local register selection
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wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
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// Register local address
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wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]};
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// Register address decode
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// Register address decode
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reg [255:0] reg_dec;
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wire [DEC_SZ-1:0] reg_dec = (IE1_D & {DEC_SZ{(reg_addr==(IE1 >>1))}}) |
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always @(per_addr)
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(IFG1_D & {DEC_SZ{(reg_addr==(IFG1 >>1))}});
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case (per_addr)
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(IE1 /2): reg_dec = IE1_D;
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(IFG1 /2): reg_dec = IFG1_D;
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default : reg_dec = {256{1'b0}};
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endcase
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// Read/Write probes
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// Read/Write probes
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wire reg_lo_write = per_we[0] & per_en;
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wire reg_lo_write = per_we[0] & reg_sel;
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wire reg_hi_write = per_we[1] & per_en;
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wire reg_hi_write = per_we[1] & reg_sel;
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wire reg_read = ~|per_we & per_en;
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wire reg_read = ~|per_we & reg_sel;
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// Read/Write vectors
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// Read/Write vectors
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wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
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wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
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wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}};
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wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
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wire [255:0] reg_rd = reg_dec & {256{reg_read}};
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wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
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//============================================================================
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//============================================================================
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// 3) REGISTERS
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// 3) REGISTERS
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//============================================================================
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//============================================================================
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// IE1 Register
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// IE1 Register
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//--------------
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//--------------
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wire [7:0] ie1;
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wire [7:0] ie1;
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wire ie1_wr = IE1[0] ? reg_hi_wr[IE1/2] : reg_lo_wr[IE1/2];
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wire ie1_wr = IE1[0] ? reg_hi_wr[IE1] : reg_lo_wr[IE1];
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wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8] : per_din[7:0];
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wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8] : per_din[7:0];
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reg nmie;
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reg nmie;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) nmie <= 1'b0;
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if (puc_rst) nmie <= 1'b0;
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else if (nmi_acc) nmie <= 1'b0;
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else if (nmi_acc) nmie <= 1'b0;
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else if (ie1_wr) nmie <= ie1_nxt[4];
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else if (ie1_wr) nmie <= ie1_nxt[4];
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reg wdtie;
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reg wdtie;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) wdtie <= 1'b0;
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if (puc_rst) wdtie <= 1'b0;
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else if (ie1_wr) wdtie <= ie1_nxt[0];
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else if (ie1_wr) wdtie <= ie1_nxt[0];
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assign ie1 = {3'b000, nmie, 3'b000, wdtie};
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assign ie1 = {3'b000, nmie, 3'b000, wdtie};
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// IFG1 Register
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// IFG1 Register
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//---------------
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//---------------
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wire [7:0] ifg1;
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wire [7:0] ifg1;
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wire ifg1_wr = IFG1[0] ? reg_hi_wr[IFG1/2] : reg_lo_wr[IFG1/2];
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wire ifg1_wr = IFG1[0] ? reg_hi_wr[IFG1] : reg_lo_wr[IFG1];
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wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8] : per_din[7:0];
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wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8] : per_din[7:0];
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reg nmiifg;
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reg nmiifg;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) nmiifg <= 1'b0;
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if (puc_rst) nmiifg <= 1'b0;
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else if (nmi_acc) nmiifg <= 1'b1;
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else if (nmi_acc) nmiifg <= 1'b1;
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else if (ifg1_wr) nmiifg <= ifg1_nxt[4];
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else if (ifg1_wr) nmiifg <= ifg1_nxt[4];
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reg wdtifg;
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reg wdtifg;
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always @ (posedge mclk or posedge por)
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always @ (posedge mclk or posedge por)
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| Line 174... |
Line 185... |
//============================================================================
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//============================================================================
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// 4) DATA OUTPUT GENERATION
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// 4) DATA OUTPUT GENERATION
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//============================================================================
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//============================================================================
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// Data output mux
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// Data output mux
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wire [15:0] ie1_rd = {8'h00, (ie1 & {8{reg_rd[IE1/2]}})} << (8 & {4{IE1[0]}});
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wire [15:0] ie1_rd = {8'h00, (ie1 & {8{reg_rd[IE1]}})} << (8 & {4{IE1[0]}});
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wire [15:0] ifg1_rd = {8'h00, (ifg1 & {8{reg_rd[IFG1/2]}})} << (8 & {4{IFG1[0]}});
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wire [15:0] ifg1_rd = {8'h00, (ifg1 & {8{reg_rd[IFG1]}})} << (8 & {4{IFG1[0]}});
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wire [15:0] per_dout = ie1_rd |
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wire [15:0] per_dout = ie1_rd |
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ifg1_rd;
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ifg1_rd;
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