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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_sfr.v] - Diff between revs 80 and 85

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Rev 80	Rev 85
Line 172...	Line 172...
`//============================================================================`	`//============================================================================`
`// 4) DATA OUTPUT GENERATION`	`// 4) DATA OUTPUT GENERATION`
`//============================================================================`	`//============================================================================`

`// Data output mux`	`// Data output mux`
`wire [15:0] ie1_rd = (ie1 & {8{reg_rd[IE1/2]}}) << (8 & {4{IE1[0]}});`	`wire [15:0] ie1_rd = {8'h00, (ie1 & {8{reg_rd[IE1/2]}})} << (8 & {4{IE1[0]}});`
`wire [15:0] ifg1_rd = (ifg1 & {8{reg_rd[IFG1/2]}}) << (8 & {4{IFG1[0]}});`	`wire [15:0] ifg1_rd = {8'h00, (ifg1 & {8{reg_rd[IFG1/2]}})} << (8 & {4{IFG1[0]}});`

`wire [15:0] per_dout = ie1_rd \|`	`wire [15:0] per_dout = ie1_rd \|`
`ifg1_rd;`	`ifg1_rd;`

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