| Line 29... |
Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 106 $
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// $Rev: 103 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 57... |
Line 57... |
nmie, // Non-maskable interrupt enable
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nmie, // Non-maskable interrupt enable
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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per_we, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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puc, // Main system reset
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puc_rst, // Main system reset
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smclk_en, // SMCLK enable
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smclk_en, // SMCLK enable
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wdtie // Watchdog timer interrupt enable
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wdtie // Watchdog timer interrupt enable
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);
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);
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// OUTPUTs
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// OUTPUTs
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Line 77... |
input aclk_en; // ACLK enable
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input aclk_en; // ACLK enable
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input dbg_freeze; // Freeze Watchdog counter
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input dbg_freeze; // Freeze Watchdog counter
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input mclk; // Main system clock
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input mclk; // Main system clock
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input nmi; // Non-maskable interrupt (asynchronous)
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input nmi; // Non-maskable interrupt (asynchronous)
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input nmie; // Non-maskable interrupt enable
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input nmie; // Non-maskable interrupt enable
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input [7:0] per_addr; // Peripheral address
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input [13:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input per_en; // Peripheral enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input puc; // Main system reset
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input puc_rst; // Main system reset
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input smclk_en; // SMCLK enable
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input smclk_en; // SMCLK enable
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input wdtie; // Watchdog timer interrupt enable
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input wdtie; // Watchdog timer interrupt enable
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//=============================================================================
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//=============================================================================
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// 1) PARAMETER DECLARATION
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// 1) PARAMETER DECLARATION
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//=============================================================================
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//=============================================================================
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// Register addresses
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// Register base address (must be aligned to decoder bit width)
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parameter WDTCTL = 9'h120;
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parameter [14:0] BASE_ADDR = 15'h0120;
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// Decoder bit width (defines how many bits are considered for address decoding)
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parameter DEC_WD = 2;
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// Register addresses offset
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parameter [DEC_WD-1:0] WDTCTL = 'h0;
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// Register one-hot decoder utilities
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parameter DEC_SZ = 2**DEC_WD;
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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// Register one-hot decoder
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// Register one-hot decoder
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parameter WDTCTL_D = (512'h1 << WDTCTL);
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parameter [DEC_SZ-1:0] WDTCTL_D = (BASE_REG << WDTCTL);
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//============================================================================
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//============================================================================
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// 2) REGISTER DECODER
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// 2) REGISTER DECODER
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//============================================================================
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//============================================================================
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// Local register selection
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wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
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// Register local address
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wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0};
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// Register address decode
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// Register address decode
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reg [511:0] reg_dec;
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wire [DEC_SZ-1:0] reg_dec = (WDTCTL_D & {DEC_SZ{(reg_addr==WDTCTL)}});
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always @(per_addr)
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case ({per_addr,1'b0})
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WDTCTL : reg_dec = WDTCTL_D;
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default: reg_dec = {512{1'b0}};
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endcase
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// Read/Write probes
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// Read/Write probes
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wire reg_write = |per_we & per_en;
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wire reg_write = |per_we & reg_sel;
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wire reg_read = ~|per_we & per_en;
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wire reg_read = ~|per_we & reg_sel;
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// Read/Write vectors
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// Read/Write vectors
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wire [511:0] reg_wr = reg_dec & {512{reg_write}};
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wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
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wire [511:0] reg_rd = reg_dec & {512{reg_read}};
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wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
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//============================================================================
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//============================================================================
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// 3) REGISTERS
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// 3) REGISTERS
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//============================================================================
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//============================================================================
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| Line 131... |
Line 141... |
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reg [7:0] wdtctl;
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reg [7:0] wdtctl;
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wire wdtctl_wr = reg_wr[WDTCTL];
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wire wdtctl_wr = reg_wr[WDTCTL];
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) wdtctl <= 8'h00;
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if (puc_rst) wdtctl <= 8'h00;
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else if (wdtctl_wr) wdtctl <= per_din[7:0] & 8'hd7;
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else if (wdtctl_wr) wdtctl <= per_din[7:0] & 8'hd7;
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wire wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a);
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wire wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a);
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wire wdttmsel = wdtctl[4];
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wire wdttmsel = wdtctl[4];
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Line 163... |
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//=============================================================================
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//=============================================================================
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// 4) NMI GENERATION
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// 4) NMI GENERATION
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//=============================================================================
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//=============================================================================
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// Synchronization state
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// Synchronization
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reg [2:0] nmi_sync;
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wire nmi_s;
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always @ (posedge mclk or posedge puc)
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`ifdef SYNC_NMI
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if (puc) nmi_sync <= 3'h0;
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omsp_sync_cell sync_cell_nmi (
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else nmi_sync <= {nmi_sync[1:0], nmi};
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.data_out (nmi_s),
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.clk (mclk),
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.data_in (nmi),
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.rst (puc_rst)
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);
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`else
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assign nmi_s = nmi;
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`endif
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// Delay
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reg nmi_dly;
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) nmi_dly <= 1'b0;
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else nmi_dly <= nmi_s;
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// Edge detection
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// Edge detection
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wire nmi_re = ~nmi_sync[2] & nmi_sync[1] & nmie;
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wire nmi_re = ~nmi_dly & nmi_s & nmie;
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wire nmi_fe = nmi_sync[2] & ~nmi_sync[1] & nmie;
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wire nmi_fe = nmi_dly & ~nmi_s & nmie;
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// NMI event
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// NMI event
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wire nmi_evt = wdtctl[6] ? nmi_fe : nmi_re;
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wire nmi_evt = wdtctl[6] ? nmi_fe : nmi_re;
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| Line 182... |
Line 205... |
//--------------------------
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//--------------------------
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reg [15:0] wdtcnt;
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reg [15:0] wdtcnt;
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wire wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_set;
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wire wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_set;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) wdtcnt <= 16'h0000;
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if (puc_rst) wdtcnt <= 16'h0000;
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else if (wdtcnt_clr) wdtcnt <= 16'h0000;
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else if (wdtcnt_clr) wdtcnt <= 16'h0000;
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else if (~wdtctl[7] & clk_src_en & ~dbg_freeze) wdtcnt <= wdtcnt+16'h0001;
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else if (~wdtctl[7] & clk_src_en & ~dbg_freeze) wdtcnt <= wdtcnt+16'h0001;
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// Interval selection mux
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// Interval selection mux
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| Line 205... |
Line 228... |
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// Watchdog event detection
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// Watchdog event detection
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//-----------------------------
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//-----------------------------
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reg wdtqn_dly;
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reg wdtqn_dly;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) wdtqn_dly <= 1'b0;
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if (puc_rst) wdtqn_dly <= 1'b0;
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else wdtqn_dly <= wdtqn;
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else wdtqn_dly <= wdtqn;
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wire wdtifg_set = (~wdtqn_dly & wdtqn) | wdtpw_error;
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wire wdtifg_set = (~wdtqn_dly & wdtqn) | wdtpw_error;
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