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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430.v] - Diff between revs 104 and 105

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430.v] - Diff between revs 104 and 105

Rev 104	Rev 105
Line 204...	Line 204...
`.inst_bw (inst_bw), // Decoded Inst: byte width`	`.inst_bw (inst_bw), // Decoded Inst: byte width`
`.inst_dest (inst_dest), // Decoded Inst: destination (one hot)`	`.inst_dest (inst_dest), // Decoded Inst: destination (one hot)`
`.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word`	`.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word`
`.inst_irq_rst (inst_irq_rst), // Decoded Inst: Reset interrupt`	`.inst_irq_rst (inst_irq_rst), // Decoded Inst: Reset interrupt`
`.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump`	`.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump`
	`.inst_mov (inst_mov), // Decoded Inst: mov instruction`
`.inst_sext (inst_sext), // Decoded Inst: source extended instruction word`	`.inst_sext (inst_sext), // Decoded Inst: source extended instruction word`
`.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic`	`.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic`
`.inst_src (inst_src), // Decoded Inst: source (one hot)`	`.inst_src (inst_src), // Decoded Inst: source (one hot)`
`.inst_type (inst_type), // Decoded Instruction type`	`.inst_type (inst_type), // Decoded Instruction type`
`.irq_acc (irq_acc), // Interrupt request accepted`	`.irq_acc (irq_acc), // Interrupt request accepted`
Line 265...	Line 266...
`.inst_bw (inst_bw), // Decoded Inst: byte width`	`.inst_bw (inst_bw), // Decoded Inst: byte width`
`.inst_dest (inst_dest), // Decoded Inst: destination (one hot)`	`.inst_dest (inst_dest), // Decoded Inst: destination (one hot)`
`.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word`	`.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word`
`.inst_irq_rst (inst_irq_rst), // Decoded Inst: reset interrupt`	`.inst_irq_rst (inst_irq_rst), // Decoded Inst: reset interrupt`
`.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump`	`.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump`
	`.inst_mov (inst_mov), // Decoded Inst: mov instruction`
`.inst_sext (inst_sext), // Decoded Inst: source extended instruction word`	`.inst_sext (inst_sext), // Decoded Inst: source extended instruction word`
`.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic`	`.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic`
`.inst_src (inst_src), // Decoded Inst: source (one hot)`	`.inst_src (inst_src), // Decoded Inst: source (one hot)`
`.inst_type (inst_type), // Decoded Instruction type`	`.inst_type (inst_type), // Decoded Instruction type`
`.mclk (mclk), // Main system clock`	`.mclk (mclk), // Main system clock`