| Line 29... |
Line 29... |
//
|
//
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// *Author(s):
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// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
|
//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 106 $
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// $Rev: 103 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 58... |
Line 58... |
per_en, // Peripheral enable (high active)
|
per_en, // Peripheral enable (high active)
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pmem_addr, // Program Memory address
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pmem_addr, // Program Memory address
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pmem_cen, // Program Memory chip enable (low active)
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pmem_cen, // Program Memory chip enable (low active)
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pmem_din, // Program Memory data input (optional)
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pmem_din, // Program Memory data input (optional)
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pmem_wen, // Program Memory write enable (low active) (optional)
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pmem_wen, // Program Memory write enable (low active) (optional)
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puc, // Main system reset
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puc_rst, // Main system reset
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smclk_en, // SMCLK enable
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smclk_en, // SMCLK enable
|
|
|
// INPUTs
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// INPUTs
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cpu_en, // Enable CPU code execution (asynchronous)
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cpu_en, // Enable CPU code execution (asynchronous)
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dbg_en, // Debug interface enable (asynchronous)
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dbg_en, // Debug interface enable (asynchronous)
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| Line 86... |
Line 86... |
output dmem_cen; // Data Memory chip enable (low active)
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output dmem_cen; // Data Memory chip enable (low active)
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output [15:0] dmem_din; // Data Memory data input
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output [15:0] dmem_din; // Data Memory data input
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output [1:0] dmem_wen; // Data Memory write enable (low active)
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output [1:0] dmem_wen; // Data Memory write enable (low active)
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output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
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output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
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output mclk; // Main system clock
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output mclk; // Main system clock
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output [7:0] per_addr; // Peripheral address
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output [13:0] per_addr; // Peripheral address
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output [15:0] per_din; // Peripheral data input
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output [15:0] per_din; // Peripheral data input
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output [1:0] per_we; // Peripheral write enable (high active)
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output [1:0] per_we; // Peripheral write enable (high active)
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output per_en; // Peripheral enable (high active)
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output per_en; // Peripheral enable (high active)
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output [`PMEM_MSB:0] pmem_addr; // Program Memory address
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output [`PMEM_MSB:0] pmem_addr; // Program Memory address
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output pmem_cen; // Program Memory chip enable (low active)
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output pmem_cen; // Program Memory chip enable (low active)
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output [15:0] pmem_din; // Program Memory data input (optional)
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output [15:0] pmem_din; // Program Memory data input (optional)
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output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
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output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
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output puc; // Main system reset
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output puc_rst; // Main system reset
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output smclk_en; // SMCLK enable
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output smclk_en; // SMCLK enable
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|
|
|
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// INPUTs
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// INPUTs
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//=========
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//=========
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| Line 122... |
Line 122... |
|
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wire [7:0] inst_ad;
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wire [7:0] inst_ad;
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wire [7:0] inst_as;
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wire [7:0] inst_as;
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wire [11:0] inst_alu;
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wire [11:0] inst_alu;
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wire inst_bw;
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wire inst_bw;
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wire inst_irq_rst;
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wire inst_mov;
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wire [15:0] inst_dest;
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wire [15:0] inst_dest;
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wire [15:0] inst_dext;
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wire [15:0] inst_dext;
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wire [15:0] inst_sext;
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wire [15:0] inst_sext;
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wire [7:0] inst_so;
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wire [7:0] inst_so;
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wire [15:0] inst_src;
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wire [15:0] inst_src;
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wire [2:0] inst_type;
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wire [2:0] inst_type;
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wire [7:0] inst_jmp;
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wire [3:0] e_state;
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wire [3:0] e_state;
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wire exec_done;
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wire exec_done;
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wire decode_noirq;
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wire cpu_en_s;
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wire cpuoff;
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wire oscoff;
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wire scg1;
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wire por;
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wire gie;
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|
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wire [15:0] eu_mab;
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wire [15:0] eu_mab;
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wire [15:0] eu_mdb_in;
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wire [15:0] eu_mdb_in;
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wire [15:0] eu_mdb_out;
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wire [15:0] eu_mdb_out;
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wire [1:0] eu_mb_wr;
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wire [1:0] eu_mb_wr;
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wire eu_mb_en;
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wire [15:0] fe_mab;
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wire [15:0] fe_mab;
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wire [15:0] fe_mdb_in;
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wire [15:0] fe_mdb_in;
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wire fe_mb_en;
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wire fe_pmem_wait;
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|
|
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wire pc_sw_wr;
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wire [15:0] pc_sw;
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wire [15:0] pc_sw;
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wire [7:0] inst_jmp;
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wire [15:0] pc;
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wire [15:0] pc;
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wire [15:0] pc_nxt;
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wire [15:0] pc_nxt;
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|
|
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wire nmie;
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wire nmi_acc;
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wire nmi_evt;
|
|
|
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wire wdtie;
|
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wire wdtifg_set;
|
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wire wdtpw_error;
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wire wdttmsel;
|
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wire wdt_irq;
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wire wdt_reset;
|
|
|
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wire dbg_clk;
|
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wire dbg_rst;
|
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wire dbg_en_s;
|
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wire dbg_halt_st;
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wire dbg_halt_cmd;
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wire dbg_halt_cmd;
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wire dbg_mem_en;
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wire dbg_mem_en;
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wire dbg_reg_wr;
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wire dbg_reg_wr;
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wire dbg_cpu_reset;
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wire dbg_cpu_reset;
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wire [15:0] dbg_mem_addr;
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wire [15:0] dbg_mem_addr;
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| Line 175... |
Line 203... |
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
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.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
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.dbg_rst (dbg_rst), // Debug unit reset
|
.dbg_rst (dbg_rst), // Debug unit reset
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.per_dout (per_dout_clk), // Peripheral data output
|
.per_dout (per_dout_clk), // Peripheral data output
|
.por (por), // Power-on reset
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.por (por), // Power-on reset
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.puc (puc), // Main system reset
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.puc_rst (puc_rst), // Main system reset
|
.smclk_en (smclk_en), // SMCLK enable
|
.smclk_en (smclk_en), // SMCLK enable
|
|
|
// INPUTs
|
// INPUTs
|
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
|
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
|
.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
|
.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
|
| Line 239... |
Line 267... |
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.nmi_evt (nmi_evt), // Non-maskable interrupt event
|
.nmi_evt (nmi_evt), // Non-maskable interrupt event
|
.pc_sw (pc_sw), // Program counter software value
|
.pc_sw (pc_sw), // Program counter software value
|
.pc_sw_wr (pc_sw_wr), // Program counter software write
|
.pc_sw_wr (pc_sw_wr), // Program counter software write
|
.puc (puc), // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
.wdt_irq (wdt_irq) // Watchdog-timer interrupt
|
.wdt_irq (wdt_irq) // Watchdog-timer interrupt
|
);
|
);
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
| Line 286... |
Line 314... |
.inst_type (inst_type), // Decoded Instruction type
|
.inst_type (inst_type), // Decoded Instruction type
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.mdb_in (eu_mdb_in), // Memory data bus input
|
.mdb_in (eu_mdb_in), // Memory data bus input
|
.pc (pc), // Program counter
|
.pc (pc), // Program counter
|
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
.puc (puc) // Main system reset
|
.puc_rst (puc_rst) // Main system reset
|
);
|
);
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 5) MEMORY BACKBONE
|
// 5) MEMORY BACKBONE
|
| Line 330... |
Line 358... |
.fe_mab (fe_mab[15:1]), // Frontend Memory address bus
|
.fe_mab (fe_mab[15:1]), // Frontend Memory address bus
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_dout (per_dout_or), // Peripheral data output
|
.per_dout (per_dout_or), // Peripheral data output
|
.pmem_dout (pmem_dout), // Program Memory data output
|
.pmem_dout (pmem_dout), // Program Memory data output
|
.puc (puc) // Main system reset
|
.puc_rst (puc_rst) // Main system reset
|
);
|
);
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 6) SPECIAL FUNCTION REGISTERS
|
// 6) SPECIAL FUNCTION REGISTERS
|
| Line 355... |
Line 383... |
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.por (por), // Power-on reset
|
.por (por), // Power-on reset
|
.puc (puc), // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
.wdtifg_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag
|
.wdtifg_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag
|
.wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag
|
.wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag
|
.wdtpw_error (wdtpw_error), // Watchdog-timer password error
|
.wdtpw_error (wdtpw_error), // Watchdog-timer password error
|
.wdttmsel (wdttmsel) // Watchdog-timer mode select
|
.wdttmsel (wdttmsel) // Watchdog-timer mode select
|
);
|
);
|
| Line 386... |
Line 414... |
.nmie (nmie), // Non-maskable interrupt enable
|
.nmie (nmie), // Non-maskable interrupt enable
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.puc (puc), // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
.smclk_en (smclk_en), // SMCLK enable
|
.smclk_en (smclk_en), // SMCLK enable
|
.wdtie (wdtie) // Watchdog-timer interrupt enable
|
.wdtie (wdtie) // Watchdog-timer interrupt enable
|
);
|
);
|
|
|
|
|
| Line 407... |
Line 435... |
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.puc (puc) // Main system reset
|
.puc_rst (puc_rst) // Main system reset
|
);
|
);
|
`else
|
`else
|
assign per_dout_mpy = 16'h0000;
|
assign per_dout_mpy = 16'h0000;
|
`endif
|
`endif
|
|
|
| Line 461... |
Line 489... |
.eu_mdb_out (eu_mdb_out), // Memory data bus output
|
.eu_mdb_out (eu_mdb_out), // Memory data bus output
|
.exec_done (exec_done), // Execution completed
|
.exec_done (exec_done), // Execution completed
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.pc (pc), // Program counter
|
.pc (pc), // Program counter
|
.puc (puc) // Main system reset
|
.puc_rst (puc_rst) // Main system reset
|
);
|
);
|
|
|
`else
|
`else
|
assign dbg_freeze = ~cpu_en_s;
|
assign dbg_freeze = ~cpu_en_s;
|
assign dbg_halt_cmd = 1'b0;
|
assign dbg_halt_cmd = 1'b0;
|
