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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430.v] - Diff between revs 136 and 155

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Line 34... Line 34...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev: 154 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
`endif
`endif
Line 49... Line 49...
 
 
// OUTPUTs
// OUTPUTs
    aclk,                          // ASIC ONLY: ACLK
    aclk,                          // ASIC ONLY: ACLK
    aclk_en,                       // FPGA ONLY: ACLK enable
    aclk_en,                       // FPGA ONLY: ACLK enable
    dbg_freeze,                    // Freeze peripherals
    dbg_freeze,                    // Freeze peripherals
 
    dbg_i2c_sda_out,                    // Debug interface: I2C SDA OUT
    dbg_uart_txd,                  // Debug interface: UART TXD
    dbg_uart_txd,                  // Debug interface: UART TXD
    dco_enable,                    // ASIC ONLY: Fast oscillator enable
    dco_enable,                    // ASIC ONLY: Fast oscillator enable
    dco_wkup,                      // ASIC ONLY: Fast oscillator wake-up (asynchronous)
    dco_wkup,                      // ASIC ONLY: Fast oscillator wake-up (asynchronous)
    dmem_addr,                     // Data Memory address
    dmem_addr,                     // Data Memory address
    dmem_cen,                      // Data Memory chip enable (low active)
    dmem_cen,                      // Data Memory chip enable (low active)
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    smclk_en,                      // FPGA ONLY: SMCLK enable
    smclk_en,                      // FPGA ONLY: SMCLK enable
 
 
// INPUTs
// INPUTs
    cpu_en,                        // Enable CPU code execution (asynchronous and non-glitchy)
    cpu_en,                        // Enable CPU code execution (asynchronous and non-glitchy)
    dbg_en,                        // Debug interface enable (asynchronous and non-glitchy)
    dbg_en,                        // Debug interface enable (asynchronous and non-glitchy)
 
    dbg_i2c_addr,                       // Debug interface: I2C Address
 
    dbg_i2c_broadcast,                  // Debug interface: I2C Broadcast Address (for multicore systems)
 
    dbg_i2c_scl,                        // Debug interface: I2C SCL
 
    dbg_i2c_sda_in,                     // Debug interface: I2C SDA IN
    dbg_uart_rxd,                  // Debug interface: UART RXD (asynchronous)
    dbg_uart_rxd,                  // Debug interface: UART RXD (asynchronous)
    dco_clk,                       // Fast oscillator (fast clock)
    dco_clk,                       // Fast oscillator (fast clock)
    dmem_dout,                     // Data Memory data output
    dmem_dout,                     // Data Memory data output
    irq,                           // Maskable interrupts
    irq,                           // Maskable interrupts
    lfxt_clk,                      // Low frequency oscillator (typ 32kHz)
    lfxt_clk,                      // Low frequency oscillator (typ 32kHz)
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    scan_enable,                   // ASIC ONLY: Scan enable (active during scan shifting)
    scan_enable,                   // ASIC ONLY: Scan enable (active during scan shifting)
    scan_mode,                     // ASIC ONLY: Scan mode
    scan_mode,                     // ASIC ONLY: Scan mode
    wkup                           // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
    wkup                           // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
);
);
 
 
 
// PARAMETERs
 
//============
 
parameter            INST_NR  = 8'h00;  // Current oMSP instance number     (for multicore systems)
 
parameter            TOTAL_NR = 8'h00;  // Total number of oMSP instances-1 (for multicore systems)
 
 
// OUTPUTs
// OUTPUTs
//=========
//============
output               aclk;         // ASIC ONLY: ACLK
output               aclk;         // ASIC ONLY: ACLK
output               aclk_en;      // FPGA ONLY: ACLK enable
output               aclk_en;      // FPGA ONLY: ACLK enable
output               dbg_freeze;   // Freeze peripherals
output               dbg_freeze;   // Freeze peripherals
 
output               dbg_i2c_sda_out;   // Debug interface: I2C SDA OUT
output               dbg_uart_txd; // Debug interface: UART TXD
output               dbg_uart_txd; // Debug interface: UART TXD
output               dco_enable;   // ASIC ONLY: Fast oscillator enable
output               dco_enable;   // ASIC ONLY: Fast oscillator enable
output               dco_wkup;     // ASIC ONLY: Fast oscillator wake-up (asynchronous)
output               dco_wkup;     // ASIC ONLY: Fast oscillator wake-up (asynchronous)
output [`DMEM_MSB:0] dmem_addr;    // Data Memory address
output [`DMEM_MSB:0] dmem_addr;    // Data Memory address
output               dmem_cen;     // Data Memory chip enable (low active)
output               dmem_cen;     // Data Memory chip enable (low active)
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output               smclk;        // ASIC ONLY: SMCLK
output               smclk;        // ASIC ONLY: SMCLK
output               smclk_en;     // FPGA ONLY: SMCLK enable
output               smclk_en;     // FPGA ONLY: SMCLK enable
 
 
 
 
// INPUTs
// INPUTs
//=========
//============
input                cpu_en;       // Enable CPU code execution (asynchronous and non-glitchy)
input                cpu_en;       // Enable CPU code execution (asynchronous and non-glitchy)
input                dbg_en;       // Debug interface enable (asynchronous and non-glitchy)
input                dbg_en;       // Debug interface enable (asynchronous and non-glitchy)
 
input          [6:0] dbg_i2c_addr;      // Debug interface: I2C Address
 
input          [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
 
input                dbg_i2c_scl;       // Debug interface: I2C SCL
 
input                dbg_i2c_sda_in;    // Debug interface: I2C SDA IN
input                dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
input                dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
input                dco_clk;      // Fast oscillator (fast clock)
input                dco_clk;      // Fast oscillator (fast clock)
input         [15:0] dmem_dout;    // Data Memory data output
input         [15:0] dmem_dout;    // Data Memory data output
input         [13:0] irq;          // Maskable interrupts
input         [13:0] irq;          // Maskable interrupts
input                lfxt_clk;     // Low frequency oscillator (typ 32kHz)
input                lfxt_clk;     // Low frequency oscillator (typ 32kHz)
Line 167... Line 182...
wire                por;
wire                por;
wire                gie;
wire                gie;
wire                mclk_enable;
wire                mclk_enable;
wire                mclk_wkup;
wire                mclk_wkup;
wire         [31:0] cpu_id;
wire         [31:0] cpu_id;
 
wire          [7:0] cpu_nr_inst  = INST_NR;
 
wire          [7:0] cpu_nr_total = TOTAL_NR;
 
 
wire         [15:0] eu_mab;
wire         [15:0] eu_mab;
wire         [15:0] eu_mdb_in;
wire         [15:0] eu_mdb_in;
wire         [15:0] eu_mdb_out;
wire         [15:0] eu_mdb_out;
wire          [1:0] eu_mb_wr;
wire          [1:0] eu_mb_wr;
Line 429... Line 446...
    .wdtie        (wdtie),         // Watchdog-timer interrupt enable
    .wdtie        (wdtie),         // Watchdog-timer interrupt enable
    .wdtifg_sw_clr(wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
    .wdtifg_sw_clr(wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
    .wdtifg_sw_set(wdtifg_sw_set), // Watchdog-timer interrupt flag software set
    .wdtifg_sw_set(wdtifg_sw_set), // Watchdog-timer interrupt flag software set
 
 
// INPUTs
// INPUTs
 
    .cpu_nr_inst  (cpu_nr_inst),   // Current oMSP instance number
 
    .cpu_nr_total (cpu_nr_total),  // Total number of oMSP instances-1
    .mclk         (mclk),          // Main system clock
    .mclk         (mclk),          // Main system clock
    .nmi          (nmi),           // Non-maskable interrupt (asynchronous)
    .nmi          (nmi),           // Non-maskable interrupt (asynchronous)
    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
    .per_addr     (per_addr),      // Peripheral address
    .per_addr     (per_addr),      // Peripheral address
    .per_din      (per_din),       // Peripheral data input
    .per_din      (per_din),       // Peripheral data input
Line 528... Line 547...
 
 
`ifdef DBG_EN
`ifdef DBG_EN
omsp_dbg dbg_0 (
omsp_dbg dbg_0 (
 
 
// OUTPUTs
// OUTPUTs
 
    .dbg_cpu_reset     (dbg_cpu_reset),     // Reset CPU from debug interface
    .dbg_freeze   (dbg_freeze),    // Freeze peripherals
    .dbg_freeze   (dbg_freeze),    // Freeze peripherals
    .dbg_halt_cmd (dbg_halt_cmd),  // Halt CPU command
    .dbg_halt_cmd (dbg_halt_cmd),  // Halt CPU command
 
    .dbg_i2c_sda_out   (dbg_i2c_sda_out),   // Debug interface: I2C SDA OUT
    .dbg_mem_addr (dbg_mem_addr),  // Debug address for rd/wr access
    .dbg_mem_addr (dbg_mem_addr),  // Debug address for rd/wr access
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
    .dbg_mem_en   (dbg_mem_en),    // Debug unit memory enable
    .dbg_mem_en   (dbg_mem_en),    // Debug unit memory enable
    .dbg_mem_wr   (dbg_mem_wr),    // Debug unit memory write
    .dbg_mem_wr   (dbg_mem_wr),    // Debug unit memory write
    .dbg_reg_wr   (dbg_reg_wr),    // Debug unit CPU register write
    .dbg_reg_wr   (dbg_reg_wr),    // Debug unit CPU register write
    .dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
 
    .dbg_uart_txd (dbg_uart_txd),  // Debug interface: UART TXD
    .dbg_uart_txd (dbg_uart_txd),  // Debug interface: UART TXD
 
 
// INPUTs
// INPUTs
    .cpu_en_s     (cpu_en_s),      // Enable CPU code execution (synchronous)
    .cpu_en_s     (cpu_en_s),      // Enable CPU code execution (synchronous)
    .cpu_id       (cpu_id),        // CPU ID
    .cpu_id       (cpu_id),        // CPU ID
 
    .cpu_nr_inst       (cpu_nr_inst),       // Current oMSP instance number
 
    .cpu_nr_total      (cpu_nr_total),      // Total number of oMSP instances-1
    .dbg_clk      (dbg_clk),       // Debug unit clock
    .dbg_clk      (dbg_clk),       // Debug unit clock
    .dbg_en_s     (dbg_en_s),      // Debug interface enable (synchronous)
    .dbg_en_s     (dbg_en_s),      // Debug interface enable (synchronous)
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
 
    .dbg_i2c_addr      (dbg_i2c_addr),      // Debug interface: I2C Address
 
    .dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
 
    .dbg_i2c_scl       (dbg_i2c_scl),       // Debug interface: I2C SCL
 
    .dbg_i2c_sda_in    (dbg_i2c_sda_in),    // Debug interface: I2C SDA IN
    .dbg_mem_din  (dbg_mem_din),   // Debug unit Memory data input
    .dbg_mem_din  (dbg_mem_din),   // Debug unit Memory data input
    .dbg_reg_din  (dbg_reg_din),   // Debug unit CPU register data input
    .dbg_reg_din  (dbg_reg_din),   // Debug unit CPU register data input
    .dbg_rst      (dbg_rst),       // Debug unit reset
    .dbg_rst      (dbg_rst),       // Debug unit reset
    .dbg_uart_rxd (dbg_uart_rxd),  // Debug interface: UART RXD (asynchronous)
    .dbg_uart_rxd (dbg_uart_rxd),  // Debug interface: UART RXD (asynchronous)
    .decode_noirq (decode_noirq),  // Frontend decode instruction
    .decode_noirq (decode_noirq),  // Frontend decode instruction
Line 562... Line 588...
    .pc           (pc),            // Program counter
    .pc           (pc),            // Program counter
    .puc_pnd_set  (puc_pnd_set)    // PUC pending set for the serial debug interface
    .puc_pnd_set  (puc_pnd_set)    // PUC pending set for the serial debug interface
);
);
 
 
`else
`else
 
assign dbg_cpu_reset   =  1'b0;
assign dbg_freeze    =  ~cpu_en_s;
assign dbg_freeze    =  ~cpu_en_s;
assign dbg_halt_cmd  =  1'b0;
assign dbg_halt_cmd  =  1'b0;
 
assign dbg_i2c_sda_out =  1'b1;
assign dbg_mem_addr  = 16'h0000;
assign dbg_mem_addr  = 16'h0000;
assign dbg_mem_dout  = 16'h0000;
assign dbg_mem_dout  = 16'h0000;
assign dbg_mem_en    =  1'b0;
assign dbg_mem_en    =  1'b0;
assign dbg_mem_wr    =  2'b00;
assign dbg_mem_wr    =  2'b00;
assign dbg_reg_wr    =  1'b0;
assign dbg_reg_wr    =  1'b0;
assign dbg_cpu_reset =  1'b0;
assign dbg_uart_txd    =  1'b1;
assign dbg_uart_txd  =  1'b0;
 
`endif
`endif
 
 
 
 
endmodule // openMSP430
endmodule // openMSP430
 
 

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