| Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $Rev: 154 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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// $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 49... |
Line 49... |
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// OUTPUTs
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// OUTPUTs
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aclk, // ASIC ONLY: ACLK
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aclk, // ASIC ONLY: ACLK
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aclk_en, // FPGA ONLY: ACLK enable
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aclk_en, // FPGA ONLY: ACLK enable
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dbg_freeze, // Freeze peripherals
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dbg_freeze, // Freeze peripherals
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dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
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dbg_uart_txd, // Debug interface: UART TXD
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dbg_uart_txd, // Debug interface: UART TXD
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dco_enable, // ASIC ONLY: Fast oscillator enable
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dco_enable, // ASIC ONLY: Fast oscillator enable
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dco_wkup, // ASIC ONLY: Fast oscillator wake-up (asynchronous)
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dco_wkup, // ASIC ONLY: Fast oscillator wake-up (asynchronous)
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dmem_addr, // Data Memory address
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dmem_addr, // Data Memory address
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dmem_cen, // Data Memory chip enable (low active)
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dmem_cen, // Data Memory chip enable (low active)
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| Line 75... |
Line 76... |
smclk_en, // FPGA ONLY: SMCLK enable
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smclk_en, // FPGA ONLY: SMCLK enable
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// INPUTs
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// INPUTs
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cpu_en, // Enable CPU code execution (asynchronous and non-glitchy)
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cpu_en, // Enable CPU code execution (asynchronous and non-glitchy)
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dbg_en, // Debug interface enable (asynchronous and non-glitchy)
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dbg_en, // Debug interface enable (asynchronous and non-glitchy)
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dbg_i2c_addr, // Debug interface: I2C Address
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dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
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dbg_i2c_scl, // Debug interface: I2C SCL
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dbg_i2c_sda_in, // Debug interface: I2C SDA IN
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dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
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dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
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dco_clk, // Fast oscillator (fast clock)
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dco_clk, // Fast oscillator (fast clock)
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dmem_dout, // Data Memory data output
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dmem_dout, // Data Memory data output
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irq, // Maskable interrupts
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irq, // Maskable interrupts
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lfxt_clk, // Low frequency oscillator (typ 32kHz)
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lfxt_clk, // Low frequency oscillator (typ 32kHz)
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| Line 89... |
Line 94... |
scan_enable, // ASIC ONLY: Scan enable (active during scan shifting)
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scan_enable, // ASIC ONLY: Scan enable (active during scan shifting)
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scan_mode, // ASIC ONLY: Scan mode
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scan_mode, // ASIC ONLY: Scan mode
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wkup // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
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wkup // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
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);
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);
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// PARAMETERs
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//============
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parameter INST_NR = 8'h00; // Current oMSP instance number (for multicore systems)
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parameter TOTAL_NR = 8'h00; // Total number of oMSP instances-1 (for multicore systems)
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// OUTPUTs
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// OUTPUTs
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//=========
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//============
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output aclk; // ASIC ONLY: ACLK
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output aclk; // ASIC ONLY: ACLK
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output aclk_en; // FPGA ONLY: ACLK enable
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output aclk_en; // FPGA ONLY: ACLK enable
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output dbg_freeze; // Freeze peripherals
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output dbg_freeze; // Freeze peripherals
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output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
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output dbg_uart_txd; // Debug interface: UART TXD
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output dbg_uart_txd; // Debug interface: UART TXD
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output dco_enable; // ASIC ONLY: Fast oscillator enable
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output dco_enable; // ASIC ONLY: Fast oscillator enable
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output dco_wkup; // ASIC ONLY: Fast oscillator wake-up (asynchronous)
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output dco_wkup; // ASIC ONLY: Fast oscillator wake-up (asynchronous)
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output [`DMEM_MSB:0] dmem_addr; // Data Memory address
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output [`DMEM_MSB:0] dmem_addr; // Data Memory address
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output dmem_cen; // Data Memory chip enable (low active)
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output dmem_cen; // Data Memory chip enable (low active)
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| Line 119... |
Line 130... |
output smclk; // ASIC ONLY: SMCLK
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output smclk; // ASIC ONLY: SMCLK
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output smclk_en; // FPGA ONLY: SMCLK enable
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output smclk_en; // FPGA ONLY: SMCLK enable
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|
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|
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// INPUTs
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// INPUTs
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//=========
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//============
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input cpu_en; // Enable CPU code execution (asynchronous and non-glitchy)
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input cpu_en; // Enable CPU code execution (asynchronous and non-glitchy)
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input dbg_en; // Debug interface enable (asynchronous and non-glitchy)
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input dbg_en; // Debug interface enable (asynchronous and non-glitchy)
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input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
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input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
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input dbg_i2c_scl; // Debug interface: I2C SCL
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input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
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input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
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input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
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input dco_clk; // Fast oscillator (fast clock)
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input dco_clk; // Fast oscillator (fast clock)
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input [15:0] dmem_dout; // Data Memory data output
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input [15:0] dmem_dout; // Data Memory data output
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input [13:0] irq; // Maskable interrupts
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input [13:0] irq; // Maskable interrupts
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input lfxt_clk; // Low frequency oscillator (typ 32kHz)
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input lfxt_clk; // Low frequency oscillator (typ 32kHz)
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| Line 167... |
Line 182... |
wire por;
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wire por;
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wire gie;
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wire gie;
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wire mclk_enable;
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wire mclk_enable;
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wire mclk_wkup;
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wire mclk_wkup;
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wire [31:0] cpu_id;
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wire [31:0] cpu_id;
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wire [7:0] cpu_nr_inst = INST_NR;
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wire [7:0] cpu_nr_total = TOTAL_NR;
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|
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wire [15:0] eu_mab;
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wire [15:0] eu_mab;
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wire [15:0] eu_mdb_in;
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wire [15:0] eu_mdb_in;
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wire [15:0] eu_mdb_out;
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wire [15:0] eu_mdb_out;
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wire [1:0] eu_mb_wr;
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wire [1:0] eu_mb_wr;
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| Line 429... |
Line 446... |
.wdtie (wdtie), // Watchdog-timer interrupt enable
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.wdtie (wdtie), // Watchdog-timer interrupt enable
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.wdtifg_sw_clr(wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
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.wdtifg_sw_clr(wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
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.wdtifg_sw_set(wdtifg_sw_set), // Watchdog-timer interrupt flag software set
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.wdtifg_sw_set(wdtifg_sw_set), // Watchdog-timer interrupt flag software set
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|
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// INPUTs
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// INPUTs
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.cpu_nr_inst (cpu_nr_inst), // Current oMSP instance number
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.cpu_nr_total (cpu_nr_total), // Total number of oMSP instances-1
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.nmi (nmi), // Non-maskable interrupt (asynchronous)
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.nmi (nmi), // Non-maskable interrupt (asynchronous)
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.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
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.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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| Line 528... |
Line 547... |
|
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`ifdef DBG_EN
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`ifdef DBG_EN
|
omsp_dbg dbg_0 (
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omsp_dbg dbg_0 (
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|
|
// OUTPUTs
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// OUTPUTs
|
|
.dbg_cpu_reset (dbg_cpu_reset), // Reset CPU from debug interface
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.dbg_freeze (dbg_freeze), // Freeze peripherals
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.dbg_freeze (dbg_freeze), // Freeze peripherals
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.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
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.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
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.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
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.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
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.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
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.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
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.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
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.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
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.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
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.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
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.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
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.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
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.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
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.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
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.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
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.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
|
|
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// INPUTs
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// INPUTs
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.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
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.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
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.cpu_id (cpu_id), // CPU ID
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.cpu_id (cpu_id), // CPU ID
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.cpu_nr_inst (cpu_nr_inst), // Current oMSP instance number
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.cpu_nr_total (cpu_nr_total), // Total number of oMSP instances-1
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.dbg_clk (dbg_clk), // Debug unit clock
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.dbg_clk (dbg_clk), // Debug unit clock
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.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
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.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
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.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
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.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
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.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
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.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
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.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
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.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
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.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
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.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
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.dbg_rst (dbg_rst), // Debug unit reset
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.dbg_rst (dbg_rst), // Debug unit reset
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.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
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.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
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.decode_noirq (decode_noirq), // Frontend decode instruction
|
.decode_noirq (decode_noirq), // Frontend decode instruction
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| Line 562... |
Line 588... |
.pc (pc), // Program counter
|
.pc (pc), // Program counter
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.puc_pnd_set (puc_pnd_set) // PUC pending set for the serial debug interface
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.puc_pnd_set (puc_pnd_set) // PUC pending set for the serial debug interface
|
);
|
);
|
|
|
`else
|
`else
|
|
assign dbg_cpu_reset = 1'b0;
|
assign dbg_freeze = ~cpu_en_s;
|
assign dbg_freeze = ~cpu_en_s;
|
assign dbg_halt_cmd = 1'b0;
|
assign dbg_halt_cmd = 1'b0;
|
|
assign dbg_i2c_sda_out = 1'b1;
|
assign dbg_mem_addr = 16'h0000;
|
assign dbg_mem_addr = 16'h0000;
|
assign dbg_mem_dout = 16'h0000;
|
assign dbg_mem_dout = 16'h0000;
|
assign dbg_mem_en = 1'b0;
|
assign dbg_mem_en = 1'b0;
|
assign dbg_mem_wr = 2'b00;
|
assign dbg_mem_wr = 2'b00;
|
assign dbg_reg_wr = 1'b0;
|
assign dbg_reg_wr = 1'b0;
|
assign dbg_cpu_reset = 1'b0;
|
assign dbg_uart_txd = 1'b1;
|
assign dbg_uart_txd = 1'b0;
|
|
`endif
|
`endif
|
|
|
|
|
endmodule // openMSP430
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endmodule // openMSP430
|
|
|
