| Line 34... |
Line 34... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 175 $
|
// $Rev: 103 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2013-01-30 22:21:42 +0100 (Wed, 30 Jan 2013) $
|
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_defines.v"
|
`include "openMSP430_defines.v"
|
`endif
|
`endif
|
| Line 56... |
Line 56... |
dco_enable, // ASIC ONLY: Fast oscillator enable
|
dco_enable, // ASIC ONLY: Fast oscillator enable
|
dco_wkup, // ASIC ONLY: Fast oscillator wake-up (asynchronous)
|
dco_wkup, // ASIC ONLY: Fast oscillator wake-up (asynchronous)
|
dmem_addr, // Data Memory address
|
dmem_addr, // Data Memory address
|
dmem_cen, // Data Memory chip enable (low active)
|
dmem_cen, // Data Memory chip enable (low active)
|
dmem_din, // Data Memory data input
|
dmem_din, // Data Memory data input
|
dmem_wen, // Data Memory write enable (low active)
|
dmem_wen, // Data Memory write byte enable (low active)
|
irq_acc, // Interrupt request accepted (one-hot signal)
|
irq_acc, // Interrupt request accepted (one-hot signal)
|
lfxt_enable, // ASIC ONLY: Low frequency oscillator enable
|
lfxt_enable, // ASIC ONLY: Low frequency oscillator enable
|
lfxt_wkup, // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
|
lfxt_wkup, // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
|
mclk, // Main system clock
|
mclk, // Main system clock
|
|
dma_dout, // Direct Memory Access data output
|
|
dma_ready, // Direct Memory Access is complete
|
|
dma_resp, // Direct Memory Access response (0:Okay / 1:Error)
|
per_addr, // Peripheral address
|
per_addr, // Peripheral address
|
per_din, // Peripheral data input
|
per_din, // Peripheral data input
|
per_we, // Peripheral write enable (high active)
|
|
per_en, // Peripheral enable (high active)
|
per_en, // Peripheral enable (high active)
|
|
per_we, // Peripheral write byte enable (high active)
|
pmem_addr, // Program Memory address
|
pmem_addr, // Program Memory address
|
pmem_cen, // Program Memory chip enable (low active)
|
pmem_cen, // Program Memory chip enable (low active)
|
pmem_din, // Program Memory data input (optional)
|
pmem_din, // Program Memory data input (optional)
|
pmem_wen, // Program Memory write enable (low active) (optional)
|
pmem_wen, // Program Memory write byte enable (low active) (optional)
|
puc_rst, // Main system reset
|
puc_rst, // Main system reset
|
smclk, // ASIC ONLY: SMCLK
|
smclk, // ASIC ONLY: SMCLK
|
smclk_en, // FPGA ONLY: SMCLK enable
|
smclk_en, // FPGA ONLY: SMCLK enable
|
|
|
// INPUTs
|
// INPUTs
|
| Line 85... |
Line 88... |
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
|
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
|
dco_clk, // Fast oscillator (fast clock)
|
dco_clk, // Fast oscillator (fast clock)
|
dmem_dout, // Data Memory data output
|
dmem_dout, // Data Memory data output
|
irq, // Maskable interrupts
|
irq, // Maskable interrupts
|
lfxt_clk, // Low frequency oscillator (typ 32kHz)
|
lfxt_clk, // Low frequency oscillator (typ 32kHz)
|
|
dma_addr, // Direct Memory Access address
|
|
dma_din, // Direct Memory Access data input
|
|
dma_en, // Direct Memory Access enable (high active)
|
|
dma_priority, // Direct Memory Access priority (0:low / 1:high)
|
|
dma_we, // Direct Memory Access write byte enable (high active)
|
|
dma_wkup, // ASIC ONLY: DMA Sub-System Wake-up (asynchronous and non-glitchy)
|
nmi, // Non-maskable interrupt (asynchronous)
|
nmi, // Non-maskable interrupt (asynchronous)
|
per_dout, // Peripheral data output
|
per_dout, // Peripheral data output
|
pmem_dout, // Program Memory data output
|
pmem_dout, // Program Memory data output
|
reset_n, // Reset Pin (low active, asynchronous and non-glitchy)
|
reset_n, // Reset Pin (low active, asynchronous and non-glitchy)
|
scan_enable, // ASIC ONLY: Scan enable (active during scan shifting)
|
scan_enable, // ASIC ONLY: Scan enable (active during scan shifting)
|
| Line 111... |
Line 120... |
output dco_enable; // ASIC ONLY: Fast oscillator enable
|
output dco_enable; // ASIC ONLY: Fast oscillator enable
|
output dco_wkup; // ASIC ONLY: Fast oscillator wake-up (asynchronous)
|
output dco_wkup; // ASIC ONLY: Fast oscillator wake-up (asynchronous)
|
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
|
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
|
output dmem_cen; // Data Memory chip enable (low active)
|
output dmem_cen; // Data Memory chip enable (low active)
|
output [15:0] dmem_din; // Data Memory data input
|
output [15:0] dmem_din; // Data Memory data input
|
output [1:0] dmem_wen; // Data Memory write enable (low active)
|
output [1:0] dmem_wen; // Data Memory write byte enable (low active)
|
output [`IRQ_NR-3:0] irq_acc; // Interrupt request accepted (one-hot signal)
|
output [`IRQ_NR-3:0] irq_acc; // Interrupt request accepted (one-hot signal)
|
output lfxt_enable; // ASIC ONLY: Low frequency oscillator enable
|
output lfxt_enable; // ASIC ONLY: Low frequency oscillator enable
|
output lfxt_wkup; // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
|
output lfxt_wkup; // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
|
output mclk; // Main system clock
|
output mclk; // Main system clock
|
|
output [15:0] dma_dout; // Direct Memory Access data output
|
|
output dma_ready; // Direct Memory Access is complete
|
|
output dma_resp; // Direct Memory Access response (0:Okay / 1:Error)
|
output [13:0] per_addr; // Peripheral address
|
output [13:0] per_addr; // Peripheral address
|
output [15:0] per_din; // Peripheral data input
|
output [15:0] per_din; // Peripheral data input
|
output [1:0] per_we; // Peripheral write enable (high active)
|
|
output per_en; // Peripheral enable (high active)
|
output per_en; // Peripheral enable (high active)
|
|
output [1:0] per_we; // Peripheral write byte enable (high active)
|
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
|
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
|
output pmem_cen; // Program Memory chip enable (low active)
|
output pmem_cen; // Program Memory chip enable (low active)
|
output [15:0] pmem_din; // Program Memory data input (optional)
|
output [15:0] pmem_din; // Program Memory data input (optional)
|
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
|
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
|
output puc_rst; // Main system reset
|
output puc_rst; // Main system reset
|
| Line 142... |
Line 154... |
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
|
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
|
input dco_clk; // Fast oscillator (fast clock)
|
input dco_clk; // Fast oscillator (fast clock)
|
input [15:0] dmem_dout; // Data Memory data output
|
input [15:0] dmem_dout; // Data Memory data output
|
input [`IRQ_NR-3:0] irq; // Maskable interrupts (14, 30 or 62)
|
input [`IRQ_NR-3:0] irq; // Maskable interrupts (14, 30 or 62)
|
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
|
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
|
|
input [15:1] dma_addr; // Direct Memory Access address
|
|
input [15:0] dma_din; // Direct Memory Access data input
|
|
input dma_en; // Direct Memory Access enable (high active)
|
|
input dma_priority; // Direct Memory Access priority (0:low / 1:high)
|
|
input [1:0] dma_we; // Direct Memory Access write byte enable (high active)
|
|
input dma_wkup; // ASIC ONLY: DMA Wake-up (asynchronous and non-glitchy)
|
input nmi; // Non-maskable interrupt (asynchronous and non-glitchy)
|
input nmi; // Non-maskable interrupt (asynchronous and non-glitchy)
|
input [15:0] per_dout; // Peripheral data output
|
input [15:0] per_dout; // Peripheral data output
|
input [15:0] pmem_dout; // Program Memory data output
|
input [15:0] pmem_dout; // Program Memory data output
|
input reset_n; // Reset Pin (active low, asynchronous and non-glitchy)
|
input reset_n; // Reset Pin (active low, asynchronous and non-glitchy)
|
input scan_enable; // ASIC ONLY: Scan enable (active during scan shifting)
|
input scan_enable; // ASIC ONLY: Scan enable (active during scan shifting)
|
| Line 179... |
Line 197... |
wire oscoff;
|
wire oscoff;
|
wire scg0;
|
wire scg0;
|
wire scg1;
|
wire scg1;
|
wire por;
|
wire por;
|
wire gie;
|
wire gie;
|
|
wire cpu_mclk;
|
|
wire dma_mclk;
|
|
wire mclk_dma_enable;
|
|
wire mclk_dma_wkup;
|
wire mclk_enable;
|
wire mclk_enable;
|
wire mclk_wkup;
|
wire mclk_wkup;
|
wire [31:0] cpu_id;
|
wire [31:0] cpu_id;
|
wire [7:0] cpu_nr_inst = INST_NR;
|
wire [7:0] cpu_nr_inst = INST_NR;
|
wire [7:0] cpu_nr_total = TOTAL_NR;
|
wire [7:0] cpu_nr_total = TOTAL_NR;
|
| Line 216... |
Line 238... |
wire wdtifg_sw_set;
|
wire wdtifg_sw_set;
|
|
|
wire dbg_clk;
|
wire dbg_clk;
|
wire dbg_rst;
|
wire dbg_rst;
|
wire dbg_en_s;
|
wire dbg_en_s;
|
wire dbg_halt_st;
|
|
wire dbg_halt_cmd;
|
wire dbg_halt_cmd;
|
wire dbg_mem_en;
|
wire dbg_mem_en;
|
wire dbg_reg_wr;
|
wire dbg_reg_wr;
|
wire dbg_cpu_reset;
|
wire dbg_cpu_reset;
|
wire [15:0] dbg_mem_addr;
|
wire [15:0] dbg_mem_addr;
|
wire [15:0] dbg_mem_dout;
|
wire [15:0] dbg_mem_dout;
|
wire [15:0] dbg_mem_din;
|
wire [15:0] dbg_mem_din;
|
wire [15:0] dbg_reg_din;
|
wire [15:0] dbg_reg_din;
|
wire [1:0] dbg_mem_wr;
|
wire [1:0] dbg_mem_wr;
|
|
|
|
wire cpu_halt_st;
|
|
wire cpu_halt_cmd;
|
wire puc_pnd_set;
|
wire puc_pnd_set;
|
|
|
wire [15:0] per_dout_or;
|
wire [15:0] per_dout_or;
|
wire [15:0] per_dout_sfr;
|
wire [15:0] per_dout_sfr;
|
wire [15:0] per_dout_wdog;
|
wire [15:0] per_dout_wdog;
|
| Line 245... |
Line 269... |
|
|
// OUTPUTs
|
// OUTPUTs
|
.aclk (aclk), // ACLK
|
.aclk (aclk), // ACLK
|
.aclk_en (aclk_en), // ACLK enablex
|
.aclk_en (aclk_en), // ACLK enablex
|
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
|
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
|
|
.cpu_mclk (cpu_mclk), // Main system CPU only clock
|
|
.dma_mclk (dma_mclk), // Main system DMA and/or CPU clock
|
.dbg_clk (dbg_clk), // Debug unit clock
|
.dbg_clk (dbg_clk), // Debug unit clock
|
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
|
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
|
.dbg_rst (dbg_rst), // Debug unit reset
|
.dbg_rst (dbg_rst), // Debug unit reset
|
.dco_enable (dco_enable), // Fast oscillator enable
|
.dco_enable (dco_enable), // Fast oscillator enable
|
.dco_wkup (dco_wkup), // Fast oscillator wake-up (asynchronous)
|
.dco_wkup (dco_wkup), // Fast oscillator wake-up (asynchronous)
|
.lfxt_enable (lfxt_enable), // Low frequency oscillator enable
|
.lfxt_enable (lfxt_enable), // Low frequency oscillator enable
|
.lfxt_wkup (lfxt_wkup), // Low frequency oscillator wake-up (asynchronous)
|
.lfxt_wkup (lfxt_wkup), // Low frequency oscillator wake-up (asynchronous)
|
.mclk (mclk), // Main system clock
|
|
.per_dout (per_dout_clk), // Peripheral data output
|
.per_dout (per_dout_clk), // Peripheral data output
|
.por (por), // Power-on reset
|
.por (por), // Power-on reset
|
.puc_pnd_set (puc_pnd_set), // PUC pending set for the serial debug interface
|
.puc_pnd_set (puc_pnd_set), // PUC pending set for the serial debug interface
|
.puc_rst (puc_rst), // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
.smclk (smclk), // SMCLK
|
.smclk (smclk), // SMCLK
|
| Line 267... |
Line 292... |
.cpuoff (cpuoff), // Turns off the CPU
|
.cpuoff (cpuoff), // Turns off the CPU
|
.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
|
.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
|
.dbg_en (dbg_en), // Debug interface enable (asynchronous)
|
.dbg_en (dbg_en), // Debug interface enable (asynchronous)
|
.dco_clk (dco_clk), // Fast oscillator (fast clock)
|
.dco_clk (dco_clk), // Fast oscillator (fast clock)
|
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
|
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
|
|
.mclk_dma_enable (mclk_dma_enable), // DMA Sub-System Clock enable
|
|
.mclk_dma_wkup (mclk_dma_wkup), // DMA Sub-System Clock wake-up (asynchronous)
|
.mclk_enable (mclk_enable), // Main System Clock enable
|
.mclk_enable (mclk_enable), // Main System Clock enable
|
.mclk_wkup (mclk_wkup), // Main System Clock wake-up (asynchronous)
|
.mclk_wkup (mclk_wkup), // Main System Clock wake-up (asynchronous)
|
.oscoff (oscoff), // Turns off LFXT1 clock input
|
.oscoff (oscoff), // Turns off LFXT1 clock input
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
| Line 282... |
Line 309... |
.scg0 (scg0), // System clock generator 1. Turns off the DCO
|
.scg0 (scg0), // System clock generator 1. Turns off the DCO
|
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
|
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
|
.wdt_reset (wdt_reset) // Watchdog-timer reset
|
.wdt_reset (wdt_reset) // Watchdog-timer reset
|
);
|
);
|
|
|
|
assign mclk = dma_mclk;
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 3) FRONTEND (<=> FETCH & DECODE)
|
// 3) FRONTEND (<=> FETCH & DECODE)
|
//=============================================================================
|
//=============================================================================
|
|
|
omsp_frontend frontend_0 (
|
omsp_frontend frontend_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
.cpu_halt_st (cpu_halt_st), // Halt/Run status from CPU
|
.decode_noirq (decode_noirq), // Frontend decode instruction
|
.decode_noirq (decode_noirq), // Frontend decode instruction
|
.e_state (e_state), // Execution state
|
.e_state (e_state), // Execution state
|
.exec_done (exec_done), // Execution completed
|
.exec_done (exec_done), // Execution completed
|
.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
|
.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
|
.inst_as (inst_as), // Decoded Inst: source addressing mode
|
.inst_as (inst_as), // Decoded Inst: source addressing mode
|
| Line 310... |
Line 339... |
.inst_src (inst_src), // Decoded Inst: source (one hot)
|
.inst_src (inst_src), // Decoded Inst: source (one hot)
|
.inst_type (inst_type), // Decoded Instruction type
|
.inst_type (inst_type), // Decoded Instruction type
|
.irq_acc (irq_acc), // Interrupt request accepted
|
.irq_acc (irq_acc), // Interrupt request accepted
|
.mab (fe_mab), // Frontend Memory address bus
|
.mab (fe_mab), // Frontend Memory address bus
|
.mb_en (fe_mb_en), // Frontend Memory bus enable
|
.mb_en (fe_mb_en), // Frontend Memory bus enable
|
|
.mclk_dma_enable (mclk_dma_enable), // DMA Sub-System Clock enable
|
|
.mclk_dma_wkup (mclk_dma_wkup), // DMA Sub-System Clock wake-up (asynchronous)
|
.mclk_enable (mclk_enable), // Main System Clock enable
|
.mclk_enable (mclk_enable), // Main System Clock enable
|
.mclk_wkup (mclk_wkup), // Main System Clock wake-up (asynchronous)
|
.mclk_wkup (mclk_wkup), // Main System Clock wake-up (asynchronous)
|
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
|
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
|
.pc (pc), // Program counter
|
.pc (pc), // Program counter
|
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
|
|
// INPUTs
|
// INPUTs
|
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
|
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
|
|
.cpu_halt_cmd (cpu_halt_cmd), // Halt CPU command
|
.cpuoff (cpuoff), // Turns off the CPU
|
.cpuoff (cpuoff), // Turns off the CPU
|
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
|
|
.dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
|
.dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
|
|
.dma_en (dma_en), // Direct Memory Access enable (high active)
|
|
.dma_wkup (dma_wkup), // DMA Sub-System Wake-up (asynchronous and non-glitchy)
|
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
|
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
|
.gie (gie), // General interrupt enable
|
.gie (gie), // General interrupt enable
|
.irq (irq), // Maskable interrupts
|
.irq (irq), // Maskable interrupts
|
.mclk (mclk), // Main system clock
|
.mclk (cpu_mclk), // Main system clock
|
.mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.nmi_pnd (nmi_pnd), // Non-maskable interrupt pending
|
.nmi_pnd (nmi_pnd), // Non-maskable interrupt pending
|
.nmi_wkup (nmi_wkup), // NMI Wakeup
|
.nmi_wkup (nmi_wkup), // NMI Wakeup
|
.pc_sw (pc_sw), // Program counter software value
|
.pc_sw (pc_sw), // Program counter software value
|
.pc_sw_wr (pc_sw_wr), // Program counter software write
|
.pc_sw_wr (pc_sw_wr), // Program counter software write
|
| Line 347... |
Line 380... |
omsp_execution_unit execution_unit_0 (
|
omsp_execution_unit execution_unit_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.cpuoff (cpuoff), // Turns off the CPU
|
.cpuoff (cpuoff), // Turns off the CPU
|
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
|
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
|
.gie (gie), // General interrupt enable
|
|
.mab (eu_mab), // Memory address bus
|
.mab (eu_mab), // Memory address bus
|
.mb_en (eu_mb_en), // Memory bus enable
|
.mb_en (eu_mb_en), // Memory bus enable
|
.mb_wr (eu_mb_wr), // Memory bus write transfer
|
.mb_wr (eu_mb_wr), // Memory bus write transfer
|
.mdb_out (eu_mdb_out), // Memory data bus output
|
.mdb_out (eu_mdb_out), // Memory data bus output
|
.oscoff (oscoff), // Turns off LFXT1 clock input
|
.oscoff (oscoff), // Turns off LFXT1 clock input
|
| Line 359... |
Line 391... |
.pc_sw_wr (pc_sw_wr), // Program counter software write
|
.pc_sw_wr (pc_sw_wr), // Program counter software write
|
.scg0 (scg0), // System clock generator 1. Turns off the DCO
|
.scg0 (scg0), // System clock generator 1. Turns off the DCO
|
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
|
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
|
|
|
// INPUTs
|
// INPUTs
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
.dbg_halt_st (cpu_halt_st), // Halt/Run status from CPU
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
|
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
|
.e_state (e_state), // Execution state
|
.e_state (e_state), // Execution state
|
.exec_done (exec_done), // Execution completed
|
.exec_done (exec_done), // Execution completed
|
|
.gie (gie), // General interrupt enable
|
.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
|
.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
|
.inst_as (inst_as), // Decoded Inst: source addressing mode
|
.inst_as (inst_as), // Decoded Inst: source addressing mode
|
.inst_alu (inst_alu), // ALU control signals
|
.inst_alu (inst_alu), // ALU control signals
|
.inst_bw (inst_bw), // Decoded Inst: byte width
|
.inst_bw (inst_bw), // Decoded Inst: byte width
|
.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
|
.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
|
| Line 377... |
Line 410... |
.inst_mov (inst_mov), // Decoded Inst: mov instruction
|
.inst_mov (inst_mov), // Decoded Inst: mov instruction
|
.inst_sext (inst_sext), // Decoded Inst: source extended instruction word
|
.inst_sext (inst_sext), // Decoded Inst: source extended instruction word
|
.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
|
.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
|
.inst_src (inst_src), // Decoded Inst: source (one hot)
|
.inst_src (inst_src), // Decoded Inst: source (one hot)
|
.inst_type (inst_type), // Decoded Instruction type
|
.inst_type (inst_type), // Decoded Instruction type
|
.mclk (mclk), // Main system clock
|
.mclk (cpu_mclk), // Main system clock
|
.mdb_in (eu_mdb_in), // Memory data bus input
|
.mdb_in (eu_mdb_in), // Memory data bus input
|
.pc (pc), // Program counter
|
.pc (pc), // Program counter
|
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
.puc_rst (puc_rst), // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
|
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
|
| Line 393... |
Line 426... |
//=============================================================================
|
//=============================================================================
|
|
|
omsp_mem_backbone mem_backbone_0 (
|
omsp_mem_backbone mem_backbone_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
|
.cpu_halt_cmd (cpu_halt_cmd), // Halt CPU command
|
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
|
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
|
.dmem_addr (dmem_addr), // Data Memory address
|
.dmem_addr (dmem_addr), // Data Memory address
|
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
|
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
|
.dmem_din (dmem_din), // Data Memory data input
|
.dmem_din (dmem_din), // Data Memory data input
|
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
|
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
|
.eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input
|
.eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input
|
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
|
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
|
|
.dma_dout (dma_dout), // Direct Memory Access data output
|
|
.dma_ready (dma_ready), // Direct Memory Access is complete
|
|
.dma_resp (dma_resp), // Direct Memory Access response (0:Okay / 1:Error)
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.pmem_addr (pmem_addr), // Program Memory address
|
.pmem_addr (pmem_addr), // Program Memory address
|
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
|
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
|
.pmem_din (pmem_din), // Program Memory data input (optional)
|
.pmem_din (pmem_din), // Program Memory data input (optional)
|
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
|
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
|
|
|
// INPUTs
|
// INPUTs
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
.cpu_halt_st (cpu_halt_st), // Halt/Run status from CPU
|
.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
|
.dbg_halt_cmd (dbg_halt_cmd), // Debug interface Halt CPU command
|
|
.dbg_mem_addr (dbg_mem_addr[15:1]), // Debug address for rd/wr access
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
|
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
|
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
|
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
|
.dmem_dout (dmem_dout), // Data Memory data output
|
.dmem_dout (dmem_dout), // Data Memory data output
|
.eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus
|
.eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus
|
.eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable
|
.eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable
|
.eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer
|
.eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer
|
.eu_mdb_out (eu_mdb_out), // Execution Unit Memory data bus output
|
.eu_mdb_out (eu_mdb_out), // Execution Unit Memory data bus output
|
.fe_mab (fe_mab[15:1]), // Frontend Memory address bus
|
.fe_mab (fe_mab[15:1]), // Frontend Memory address bus
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
.mclk (mclk), // Main system clock
|
.mclk (dma_mclk), // Main system clock
|
|
.dma_addr (dma_addr), // Direct Memory Access address
|
|
.dma_din (dma_din), // Direct Memory Access data input
|
|
.dma_en (dma_en), // Direct Memory Access enable (high active)
|
|
.dma_priority (dma_priority), // Direct Memory Access priority (0:low / 1:high)
|
|
.dma_we (dma_we), // Direct Memory Access write byte enable (high active)
|
.per_dout (per_dout_or), // Peripheral data output
|
.per_dout (per_dout_or), // Peripheral data output
|
.pmem_dout (pmem_dout), // Program Memory data output
|
.pmem_dout (pmem_dout), // Program Memory data output
|
.puc_rst (puc_rst), // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
|
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
|
);
|
);
|
|
|
|
wire UNUSED_fe_mab_0 = fe_mab[0];
|
|
|
//=============================================================================
|
//=============================================================================
|
// 6) SPECIAL FUNCTION REGISTERS
|
// 6) SPECIAL FUNCTION REGISTERS
|
//=============================================================================
|
//=============================================================================
|
omsp_sfr sfr_0 (
|
omsp_sfr sfr_0 (
|
| Line 448... |
Line 492... |
.wdtifg_sw_set(wdtifg_sw_set), // Watchdog-timer interrupt flag software set
|
.wdtifg_sw_set(wdtifg_sw_set), // Watchdog-timer interrupt flag software set
|
|
|
// INPUTs
|
// INPUTs
|
.cpu_nr_inst (cpu_nr_inst), // Current oMSP instance number
|
.cpu_nr_inst (cpu_nr_inst), // Current oMSP instance number
|
.cpu_nr_total (cpu_nr_total), // Total number of oMSP instances-1
|
.cpu_nr_total (cpu_nr_total), // Total number of oMSP instances-1
|
.mclk (mclk), // Main system clock
|
.mclk (dma_mclk), // Main system clock
|
.nmi (nmi), // Non-maskable interrupt (asynchronous)
|
.nmi (nmi), // Non-maskable interrupt (asynchronous)
|
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
|
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
| Line 480... |
Line 524... |
|
|
// INPUTs
|
// INPUTs
|
.aclk (aclk), // ACLK
|
.aclk (aclk), // ACLK
|
.aclk_en (aclk_en), // ACLK enable
|
.aclk_en (aclk_en), // ACLK enable
|
.dbg_freeze (dbg_freeze), // Freeze Watchdog counter
|
.dbg_freeze (dbg_freeze), // Freeze Watchdog counter
|
.mclk (mclk), // Main system clock
|
.mclk (dma_mclk), // Main system clock
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.por (por), // Power-on reset
|
.por (por), // Power-on reset
|
| Line 503... |
Line 547... |
assign wdt_irq = 1'b0;
|
assign wdt_irq = 1'b0;
|
assign wdt_reset = 1'b0;
|
assign wdt_reset = 1'b0;
|
assign wdt_wkup = 1'b0;
|
assign wdt_wkup = 1'b0;
|
assign wdtifg = 1'b0;
|
assign wdtifg = 1'b0;
|
assign wdtnmies = 1'b0;
|
assign wdtnmies = 1'b0;
|
|
wire UNUSED_por = por;
|
|
wire UNUSED_wdtie = wdtie;
|
|
wire UNUSED_wdtifg_sw_clr = wdtifg_sw_clr;
|
|
wire UNUSED_wdtifg_sw_set = wdtifg_sw_set;
|
`endif
|
`endif
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 8) HARDWARE MULTIPLIER
|
// 8) HARDWARE MULTIPLIER
|
| Line 516... |
Line 564... |
|
|
// OUTPUTs
|
// OUTPUTs
|
.per_dout (per_dout_mpy), // Peripheral data output
|
.per_dout (per_dout_mpy), // Peripheral data output
|
|
|
// INPUTs
|
// INPUTs
|
.mclk (mclk), // Main system clock
|
.mclk (dma_mclk), // Main system clock
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.puc_rst (puc_rst), // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
| Line 565... |
Line 613... |
.cpu_id (cpu_id), // CPU ID
|
.cpu_id (cpu_id), // CPU ID
|
.cpu_nr_inst (cpu_nr_inst), // Current oMSP instance number
|
.cpu_nr_inst (cpu_nr_inst), // Current oMSP instance number
|
.cpu_nr_total (cpu_nr_total), // Total number of oMSP instances-1
|
.cpu_nr_total (cpu_nr_total), // Total number of oMSP instances-1
|
.dbg_clk (dbg_clk), // Debug unit clock
|
.dbg_clk (dbg_clk), // Debug unit clock
|
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
|
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
.dbg_halt_st (cpu_halt_st), // Halt/Run status from CPU
|
.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
|
.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
|
.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
|
.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
|
.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
|
.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
|
.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
|
.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
|
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
|
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
|
| Line 594... |
Line 642... |
assign dbg_mem_dout = 16'h0000;
|
assign dbg_mem_dout = 16'h0000;
|
assign dbg_mem_en = 1'b0;
|
assign dbg_mem_en = 1'b0;
|
assign dbg_mem_wr = 2'b00;
|
assign dbg_mem_wr = 2'b00;
|
assign dbg_reg_wr = 1'b0;
|
assign dbg_reg_wr = 1'b0;
|
assign dbg_uart_txd = 1'b1;
|
assign dbg_uart_txd = 1'b1;
|
|
wire UNUSED_decode_noirq = decode_noirq;
|
|
wire [31:0] UNUSED_cpu_id = cpu_id;
|
|
wire UNUSED_eu_mab_0 = eu_mab[0];
|
|
wire UNUSED_dbg_clk = dbg_clk;
|
|
wire UNUSED_dbg_rst = dbg_rst;
|
|
wire UNUSED_dbg_en_s = dbg_en_s;
|
|
wire [15:0] UNUSED_dbg_mem_din = dbg_mem_din;
|
|
wire [15:0] UNUSED_dbg_reg_din = dbg_reg_din;
|
|
wire UNUSED_puc_pnd_set = puc_pnd_set;
|
|
wire [6:0] UNUSED_dbg_i2c_addr = dbg_i2c_addr;
|
|
wire [6:0] UNUSED_dbg_i2c_broadcast = dbg_i2c_broadcast;
|
|
wire UNUSED_dbg_i2c_scl = dbg_i2c_scl;
|
|
wire UNUSED_dbg_i2c_sda_in = dbg_i2c_sda_in;
|
|
wire UNUSED_dbg_uart_rxd = dbg_uart_rxd;
|
`endif
|
`endif
|
|
|
|
|
endmodule // openMSP430
|
endmodule // openMSP430
|
|
|
