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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430.v] - Diff between revs 80 and 86

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Rev 80 Rev 86
Line 137... Line 137...
wire         [15:0] pc_sw;
wire         [15:0] pc_sw;
wire          [7:0] inst_jmp;
wire          [7:0] inst_jmp;
wire         [15:0] pc;
wire         [15:0] pc;
wire         [15:0] pc_nxt;
wire         [15:0] pc_nxt;
 
 
 
wire                dbg_halt_cmd;
 
wire                dbg_mem_en;
 
wire                dbg_reg_wr;
 
wire                dbg_reset;
wire         [15:0] dbg_mem_addr;
wire         [15:0] dbg_mem_addr;
wire         [15:0] dbg_mem_dout;
wire         [15:0] dbg_mem_dout;
wire         [15:0] dbg_mem_din;
wire         [15:0] dbg_mem_din;
wire         [15:0] dbg_reg_din;
wire         [15:0] dbg_reg_din;
wire          [1:0] dbg_mem_wr;
wire          [1:0] dbg_mem_wr;

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