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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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// Copyright (C) 2009 , Olivier Girard
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//
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//
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// This source file may be used and distributed without restriction provided
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// Redistribution and use in source and binary forms, with or without
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// that this copyright statement is not removed from the file and that any
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// modification, are permitted provided that the following conditions
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// derivative work contains the original copyright notice and the associated
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// are met:
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// disclaimer.
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// * Redistributions of source code must retain the above copyright
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//
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// notice, this list of conditions and the following disclaimer.
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// This source file is free software; you can redistribute it and/or modify
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// * Redistributions in binary form must reproduce the above copyright
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// it under the terms of the GNU Lesser General Public License as published
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// notice, this list of conditions and the following disclaimer in the
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// by the Free Software Foundation; either version 2.1 of the License, or
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// documentation and/or other materials provided with the distribution.
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// (at your option) any later version.
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// * Neither the name of the authors nor the names of its contributors
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//
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// may be used to endorse or promote products derived from this software
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// without specific prior written permission.
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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//
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// License for more details.
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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//
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// You should have received a copy of the GNU Lesser General Public License
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// along with this source; if not, write to the Free Software Foundation,
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: openMSP430_defines.v
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// *File Name: openMSP430_defines.v
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//
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//
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| Line 101... |
Line 106... |
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
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// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
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//============================================================================
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//============================================================================
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//============================================================================
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//============================================================================
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//-------------------------------------------------------
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//-------------------------------------------------------
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// Custom user version number
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//-------------------------------------------------------
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// This 5 bit field can be freely used in order to allow
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// custom identification of the system through the debug
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// interface.
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// (see CPU_ID.USER_VERSION field in the documentation)
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//-------------------------------------------------------
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`define USER_VERSION 5'b00011
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//-------------------------------------------------------
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// Include/Exclude Watchdog timer
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//-------------------------------------------------------
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// When excluded, the following functionality will be
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// lost:
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// - Watchog (both interval and watchdog modes)
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// - NMI interrupt edge selection
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// - Possibility to generate a software PUC reset
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//-------------------------------------------------------
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`define WATCHDOG
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///-------------------------------------------------------
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// Include/Exclude Non-Maskable-Interrupt support
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//-------------------------------------------------------
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`define NMI
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//-------------------------------------------------------
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// Input synchronizers
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//-------------------------------------------------------
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// In some cases, the asynchronous input ports might
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// already be synchronized externally.
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// If an extensive CDC design review showed that this
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// is really the case, the individual synchronizers
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// can be disabled with the following defines.
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//
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// Notes:
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// - all three signals are all sampled in the MCLK domain
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//
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// - the dbg_en signal reset the debug interface
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// when 0. Therefore make sure it is glitch free.
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//
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//-------------------------------------------------------
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`define SYNC_NMI
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`define SYNC_CPU_EN
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`define SYNC_DBG_EN
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//-------------------------------------------------------
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// Peripheral Memory Space:
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// Peripheral Memory Space:
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//-------------------------------------------------------
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//-------------------------------------------------------
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// The original MSP430 architecture map the peripherals
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// The original MSP430 architecture map the peripherals
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// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
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// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
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// The following defines allow you to expand this space
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// The following defines allow you to expand this space
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Line 180... |
//-------------------------------------------------------
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//-------------------------------------------------------
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// Defines the debugger CPU_CTL.RST_BRK_EN reset value
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// Defines the debugger CPU_CTL.RST_BRK_EN reset value
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// (CPU break on PUC reset)
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// (CPU break on PUC reset)
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//-------------------------------------------------------
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//-------------------------------------------------------
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// When defined, the CPU will automatically break after
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// When defined, the CPU will automatically break after
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// a PUC occurrence by default. This is typically usefull
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// a PUC occurrence by default. This is typically useful
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// when the program memory can only be initialized through
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// when the program memory can only be initialized through
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// the serial debug interface.
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// the serial debug interface.
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//-------------------------------------------------------
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//-------------------------------------------------------
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//`define DBG_RST_BRK_EN
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`define DBG_RST_BRK_EN
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//-------------------------------------------------------
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// Custom user version number
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//-------------------------------------------------------
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// This 5 bit field can be freely used in order to allow
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// custom identification of the system through the debug
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// interface.
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// (see CPU_ID.USER_VERSION field in the documentation)
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//-------------------------------------------------------
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`define USER_VERSION 5'b00011
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//============================================================================
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//============================================================================
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//============================================================================
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//============================================================================
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// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
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// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
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Line 200... |
// you are doing :-P
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// you are doing :-P
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//
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//
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//============================================================================
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//============================================================================
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//-------------------------------------------------------
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//-------------------------------------------------------
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// Number of hardware breakpoint units (each unit contains
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// Number of hardware breakpoint/watchpoint units
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// two hardware address breakpoints):
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// (each unit contains two hardware addresses available
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// for breakpoints or watchpoints):
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// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
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// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
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// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
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// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
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// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
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// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
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// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
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// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
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//-------------------------------------------------------
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//-------------------------------------------------------
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// Please keep in mind that hardware breakpoints only
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// Please keep in mind that hardware breakpoints only
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// make sense whenever the program memory is not an SRAM
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// make sense whenever the program memory is not an SRAM
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// (i.e. Flash/OTP/ROM/...) or when you are interested
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// (i.e. Flash/OTP/ROM/...) or when you are interested
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// in data breakpoints (btw. not supported by GDB).
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// in data breakpoints.
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//-------------------------------------------------------
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//-------------------------------------------------------
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//`define DBG_HWBRK_0
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//`define DBG_HWBRK_0
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//`define DBG_HWBRK_1
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//`define DBG_HWBRK_1
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//`define DBG_HWBRK_2
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//`define DBG_HWBRK_2
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//`define DBG_HWBRK_3
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//`define DBG_HWBRK_3
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Line 231... |
//-------------------------------------------------------
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//-------------------------------------------------------
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//`define DBG_HWBRK_RANGE
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//`define DBG_HWBRK_RANGE
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//-------------------------------------------------------
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//-------------------------------------------------------
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// Input synchronizers
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// ASIC version
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//-------------------------------------------------------
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//-------------------------------------------------------
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// In some cases, the asynchronous input ports might
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// When uncommented, this define will enable the
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// already be synchronized externally.
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// ASIC system configuration section (see below) and
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// If an extensive CDC design review showed that this
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// will activate scan support for production test.
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// is really the case, the individual synchronizers
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// can be disabled with the following defines.
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//
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//
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// Notes:
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// WARNING: if you target an FPGA, leave this define
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// - the dbg_en signal will reset the debug interface
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// commented.
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// when 0. Therefore make sure it is glitch free.
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//
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// - the dbg_uart_rxd synchronizer must be set to 1
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// when its reset is active.
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//-------------------------------------------------------
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//-------------------------------------------------------
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`define SYNC_CPU_EN
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//`define ASIC
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`define SYNC_DBG_EN
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`define SYNC_DBG_UART_RXD
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`define SYNC_NMI
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//============================================================================
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//============================================================================
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// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
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//============================================================================
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//============================================================================
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`ifdef ASIC
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//===============================================================
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// FINE GRAINED CLOCK GATING
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//===============================================================
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//-------------------------------------------------------
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// When uncommented, this define will enable the fine
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// grained clock gating of all registers in the core.
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//-------------------------------------------------------
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`define CLOCK_GATING
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//===============================================================
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// LFXT CLOCK DOMAIN
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//===============================================================
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//-------------------------------------------------------
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// When uncommented, this define will enable the lfxt_clk
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// clock domain.
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// When commented out, the whole chip is clocked with dco_clk.
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//-------------------------------------------------------
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`define LFXT_DOMAIN
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//===============================================================
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// CLOCK MUXES
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//===============================================================
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//-------------------------------------------------------
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// MCLK: Clock Mux
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//-------------------------------------------------------
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// When uncommented, this define will enable the
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// MCLK clock MUX allowing the selection between
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// DCO_CLK and LFXT_CLK with the BCSCTL2.SELMx register.
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// When commented, DCO_CLK is selected.
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//-------------------------------------------------------
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`define MCLK_MUX
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//-------------------------------------------------------
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// SMCLK: Clock Mux
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//-------------------------------------------------------
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// When uncommented, this define will enable the
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// SMCLK clock MUX allowing the selection between
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// DCO_CLK and LFXT_CLK with the BCSCTL2.SELS register.
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// When commented, DCO_CLK is selected.
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//-------------------------------------------------------
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`define SMCLK_MUX
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//-------------------------------------------------------
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// WATCHDOG: Clock Mux
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//-------------------------------------------------------
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// When uncommented, this define will enable the
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// Watchdog clock MUX allowing the selection between
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// ACLK and SMCLK with the WDTCTL.WDTSSEL register.
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// When commented out, ACLK is selected if the
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// WATCHDOG_NOMUX_ACLK define is uncommented, SMCLK is
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// selected otherwise.
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//-------------------------------------------------------
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`define WATCHDOG_MUX
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//`define WATCHDOG_NOMUX_ACLK
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//===============================================================
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// CLOCK DIVIDERS
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//===============================================================
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//-------------------------------------------------------
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// MCLK: Clock divider
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//-------------------------------------------------------
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// When uncommented, this define will enable the
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// MCLK clock divider (/1/2/4/8)
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//-------------------------------------------------------
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`define MCLK_DIVIDER
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//-------------------------------------------------------
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// SMCLK: Clock divider (/1/2/4/8)
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//-------------------------------------------------------
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// When uncommented, this define will enable the
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// SMCLK clock divider
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//-------------------------------------------------------
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`define SMCLK_DIVIDER
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//-------------------------------------------------------
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// ACLK: Clock divider (/1/2/4/8)
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//-------------------------------------------------------
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// When uncommented, this define will enable the
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// ACLK clock divider
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//-------------------------------------------------------
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`define ACLK_DIVIDER
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//===============================================================
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// LOW POWER MODES
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//===============================================================
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//-------------------------------------------------------
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// LOW POWER MODE: CPUOFF
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//-------------------------------------------------------
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// When uncommented, this define will include the
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// clock gate allowing to switch off MCLK in
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// all low power modes: LPM0, LPM1, LPM2, LPM3, LPM4
|
|
//-------------------------------------------------------
|
|
`define CPUOFF_EN
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|
|
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//-------------------------------------------------------
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// LOW POWER MODE: SCG0
|
|
//-------------------------------------------------------
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// When uncommented, this define will enable the
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// DCO_ENABLE/WKUP port control (always 1 when commented).
|
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// This allows to switch off the DCO oscillator in the
|
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// following low power modes: LPM1, LPM3, LPM4
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|
//-------------------------------------------------------
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`define SCG0_EN
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|
|
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//-------------------------------------------------------
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// LOW POWER MODE: SCG1
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|
//-------------------------------------------------------
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// When uncommented, this define will include the
|
|
// clock gate allowing to switch off SMCLK in
|
|
// the following low power modes: LPM2, LPM3, LPM4
|
|
//-------------------------------------------------------
|
|
`define SCG1_EN
|
|
|
|
//-------------------------------------------------------
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// LOW POWER MODE: OSCOFF
|
|
//-------------------------------------------------------
|
|
// When uncommented, this define will include the
|
|
// LFXT_CLK clock gate and enable the LFXT_ENABLE/WKUP
|
|
// port control (always 1 when commented).
|
|
// This allows to switch off the low frequency oscillator
|
|
// in the following low power modes: LPM4
|
|
//-------------------------------------------------------
|
|
`define OSCOFF_EN
|
|
|
|
|
|
|
|
`endif
|
|
|
//==========================================================================//
|
//==========================================================================//
|
//==========================================================================//
|
//==========================================================================//
|
//==========================================================================//
|
//==========================================================================//
|
//==========================================================================//
|
//==========================================================================//
|
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
|
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
|
| Line 434... |
Line 613... |
`define I_EXT1 3'h3
|
`define I_EXT1 3'h3
|
`define I_EXT2 3'h4
|
`define I_EXT2 3'h4
|
`define I_IDLE 3'h5
|
`define I_IDLE 3'h5
|
|
|
// Execution state machine
|
// Execution state machine
|
`define E_IRQ_0 4'h0
|
// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
|
|
`define E_IRQ_0 4'h2
|
`define E_IRQ_1 4'h1
|
`define E_IRQ_1 4'h1
|
`define E_IRQ_2 4'h2
|
`define E_IRQ_2 4'h0
|
`define E_IRQ_3 4'h3
|
`define E_IRQ_3 4'h3
|
`define E_IRQ_4 4'h4
|
`define E_IRQ_4 4'h4
|
`define E_SRC_AD 4'h5
|
`define E_SRC_AD 4'h5
|
`define E_SRC_RD 4'h6
|
`define E_SRC_RD 4'h6
|
`define E_SRC_WR 4'h7
|
`define E_SRC_WR 4'h7
|
| Line 496... |
Line 676... |
|
|
// Basic clock module: BCSCTL1 Control Register
|
// Basic clock module: BCSCTL1 Control Register
|
`define DIVAx 5:4
|
`define DIVAx 5:4
|
|
|
// Basic clock module: BCSCTL2 Control Register
|
// Basic clock module: BCSCTL2 Control Register
|
|
`define SELMx 7
|
|
`define DIVMx 5:4
|
`define SELS 3
|
`define SELS 3
|
`define DIVSx 2:1
|
`define DIVSx 2:1
|
|
|
|
// MCLK Clock gate
|
|
`ifdef CPUOFF_EN
|
|
`define MCLK_CGATE
|
|
`else
|
|
`ifdef MCLK_DIVIDER
|
|
`define MCLK_CGATE
|
|
`endif
|
|
`endif
|
|
|
|
// SMCLK Clock gate
|
|
`ifdef SCG1_EN
|
|
`define SMCLK_CGATE
|
|
`else
|
|
`ifdef SMCLK_DIVIDER
|
|
`define SMCLK_CGATE
|
|
`endif
|
|
`endif
|
|
|
//
|
//
|
// DEBUG INTERFACE EXTRA CONFIGURATION
|
// DEBUG INTERFACE EXTRA CONFIGURATION
|
//======================================
|
//======================================
|
|
|
// Debug interface: CPU version
|
// Debug interface: CPU version
|
`define CPU_VERSION 3'h1
|
`define CPU_VERSION 3'h2
|
|
|
// Debug interface: Software breakpoint opcode
|
// Debug interface: Software breakpoint opcode
|
`define DBG_SWBRK_OP 16'h4343
|
`define DBG_SWBRK_OP 16'h4343
|
|
|
// Debug UART interface auto data synchronization
|
// Debug UART interface auto data synchronization
|
| Line 541... |
Line 740... |
// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
|
// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
|
//
|
//
|
`define DBG_UART
|
`define DBG_UART
|
//`define DBG_JTAG
|
//`define DBG_JTAG
|
|
|
|
// Debug interface input synchronizer
|
|
`define SYNC_DBG_UART_RXD
|
|
|
// Enable/Disable the hardware breakpoint RANGE mode
|
// Enable/Disable the hardware breakpoint RANGE mode
|
`ifdef DBG_HWBRK_RANGE
|
`ifdef DBG_HWBRK_RANGE
|
`define HWBRK_RANGE 1'b1
|
`define HWBRK_RANGE 1'b1
|
`else
|
`else
|
`define HWBRK_RANGE 1'b0
|
`define HWBRK_RANGE 1'b0
|
| Line 575... |
Line 777... |
// If uncommented, the following define selects
|
// If uncommented, the following define selects
|
// the 16x16 multiplier (1 cycle) instead of the
|
// the 16x16 multiplier (1 cycle) instead of the
|
// default 16x8 multplier (2 cycles)
|
// default 16x8 multplier (2 cycles)
|
//`define MPY_16x16
|
//`define MPY_16x16
|
|
|
No newline at end of file
|
No newline at end of file
|
|
//======================================
|
|
// CONFIGURATION CHECKS
|
|
//======================================
|
|
`ifdef LFXT_DOMAIN
|
|
`else
|
|
`ifdef MCLK_MUX
|
|
CONFIGURATION ERROR: THE MCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
|
`endif
|
|
`ifdef SMCLK_MUX
|
|
CONFIGURATION ERROR: THE SMCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
|
`endif
|
|
`ifdef WATCHDOG_MUX
|
|
CONFIGURATION ERROR: THE WATCHDOG_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
|
`else
|
|
`ifdef WATCHDOG_NOMUX_ACLK
|
|
CONFIGURATION ERROR: THE WATCHDOG_NOMUX_ACLK CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
|
`endif
|
|
`endif
|
|
`ifdef OSCOFF_EN
|
|
CONFIGURATION ERROR: THE OSCOFF LOW POWER MODE CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
|
`endif
|
|
`endif
|
|
|
No newline at end of file
|
No newline at end of file
|
