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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [periph/] [omsp_timerA.v] - Diff between revs 111 and 136

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//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
// Copyright (C) 2009 , Olivier Girard
//
//
// This source file may be used and distributed without restriction provided
// Redistribution and use in source and binary forms, with or without
// that this copyright statement is not removed from the file and that any
// modification, are permitted provided that the following conditions
// derivative work contains the original copyright notice and the associated
// are met:
// disclaimer.
//     * Redistributions of source code must retain the above copyright
 
//       notice, this list of conditions and the following disclaimer.
 
//     * Redistributions in binary form must reproduce the above copyright
 
//       notice, this list of conditions and the following disclaimer in the
 
//       documentation and/or other materials provided with the distribution.
 
//     * Neither the name of the authors nor the names of its contributors
 
//       may be used to endorse or promote products derived from this software
 
//       without specific prior written permission.
//
//
// This source file is free software; you can redistribute it and/or modify
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// it under the terms of the GNU Lesser General Public License as published
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// by the Free Software Foundation; either version 2.1 of the License, or
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// (at your option) any later version.
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
//
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// This source is distributed in the hope that it will be useful, but WITHOUT
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// License for more details.
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// You should have received a copy of the GNU Lesser General Public License
// THE POSSIBILITY OF SUCH DAMAGE
// along with this source; if not, write to the Free Software Foundation,
 
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
 
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//
//
// *File Name: omsp_timerA.v
// *File Name: omsp_timerA.v
// 
// 
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                       TACCTL2    = 'h66,
                       TACCTL2    = 'h66,
                       TACCR2     = 'h76,
                       TACCR2     = 'h76,
                       TAIV       = 'h2E;
                       TAIV       = 'h2E;
 
 
// Register one-hot decoder utilities
// Register one-hot decoder utilities
parameter              DEC_SZ     =  2**DEC_WD;
parameter              DEC_SZ     =  (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG   =  {{DEC_SZ-1{1'b0}}, 1'b1};
parameter [DEC_SZ-1:0] BASE_REG   =  {{DEC_SZ-1{1'b0}}, 1'b1};
 
 
// Register one-hot decoder
// Register one-hot decoder
parameter [DEC_SZ-1:0] TACTL_D    = (BASE_REG << TACTL),
parameter [DEC_SZ-1:0] TACTL_D    = (BASE_REG << TACTL),
                       TAR_D      = (BASE_REG << TAR),
                       TAR_D      = (BASE_REG << TAR),
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wire taclk_s;
wire taclk_s;
wire inclk_s;
wire inclk_s;
 
 
omsp_sync_cell sync_cell_taclk (
omsp_sync_cell sync_cell_taclk (
    .data_out (taclk_s),
    .data_out (taclk_s),
    .clk      (mclk),
 
    .data_in  (taclk),
    .data_in  (taclk),
 
    .clk       (mclk),
    .rst      (puc_rst)
    .rst      (puc_rst)
);
);
 
 
omsp_sync_cell sync_cell_inclk (
omsp_sync_cell sync_cell_inclk (
    .data_out (inclk_s),
    .data_out (inclk_s),
    .clk      (mclk),
 
    .data_in  (inclk),
    .data_in  (inclk),
 
    .clk       (mclk),
    .rst      (puc_rst)
    .rst      (puc_rst)
);
);
 
 
 
 
// Clock edge detection (TACLK & INCLK)
// Clock edge detection (TACLK & INCLK)
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wire cci1_s;
wire cci1_s;
wire cci2_s;
wire cci2_s;
 
 
omsp_sync_cell sync_cell_cci0 (
omsp_sync_cell sync_cell_cci0 (
    .data_out (cci0_s),
    .data_out (cci0_s),
    .clk      (mclk),
 
    .data_in  (cci0),
    .data_in  (cci0),
 
    .clk      (mclk),
    .rst      (puc_rst)
    .rst      (puc_rst)
);
);
omsp_sync_cell sync_cell_cci1 (
omsp_sync_cell sync_cell_cci1 (
    .data_out (cci1_s),
    .data_out (cci1_s),
    .clk      (mclk),
 
    .data_in  (cci1),
    .data_in  (cci1),
 
    .clk      (mclk),
    .rst      (puc_rst)
    .rst      (puc_rst)
);
);
omsp_sync_cell sync_cell_cci2 (
omsp_sync_cell sync_cell_cci2 (
    .data_out (cci2_s),
    .data_out (cci2_s),
    .clk      (mclk),
 
    .data_in  (cci2),
    .data_in  (cci2),
 
    .clk      (mclk),
    .rst      (puc_rst)
    .rst      (puc_rst)
);
);
 
 
// Register CCIx for edge detection
// Register CCIx for edge detection
reg cci0_dly;
reg cci0_dly;

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