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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [periph/] [template_periph_16b.v] - Diff between revs 104 and 107

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Rev 104 Rev 107
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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev: 106 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
 
`else
 
`include "openMSP430_defines.v"
 
`endif
 
 
 
module  template_periph_16b (
module  template_periph_16b (
 
 
// OUTPUTs
// OUTPUTs
    per_dout,                       // Peripheral data output
    per_dout,                       // Peripheral data output
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// INPUTs
// INPUTs
    mclk,                           // Main system clock
    mclk,                           // Main system clock
    per_addr,                       // Peripheral address
    per_addr,                       // Peripheral address
    per_din,                        // Peripheral data input
    per_din,                        // Peripheral data input
    per_en,                         // Peripheral enable (high active)
    per_en,                         // Peripheral enable (high active)
    per_wen,                        // Peripheral write enable (high active)
    per_we,                         // Peripheral write enable (high active)
    puc                             // Main system reset
    puc                             // Main system reset
);
);
 
 
// OUTPUTs
// OUTPUTs
//=========
//=========
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//=========
//=========
input               mclk;           // Main system clock
input               mclk;           // Main system clock
input         [7:0] per_addr;       // Peripheral address
input         [7:0] per_addr;       // Peripheral address
input        [15:0] per_din;        // Peripheral data input
input        [15:0] per_din;        // Peripheral data input
input               per_en;         // Peripheral enable (high active)
input               per_en;         // Peripheral enable (high active)
input         [1:0] per_wen;        // Peripheral write enable (high active)
input         [1:0] per_we;         // Peripheral write enable (high active)
input               puc;            // Main system reset
input               puc;            // Main system reset
 
 
 
 
//=============================================================================
//=============================================================================
// 1)  PARAMETER DECLARATION
// 1)  PARAMETER DECLARATION
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    CNTRL4 :     reg_dec  =  CNTRL4_D;
    CNTRL4 :     reg_dec  =  CNTRL4_D;
    default:     reg_dec  =  {512{1'b0}};
    default:     reg_dec  =  {512{1'b0}};
  endcase
  endcase
 
 
// Read/Write probes
// Read/Write probes
wire         reg_write =  |per_wen   & per_en;
wire         reg_write =  |per_we & per_en;
wire         reg_read  = ~|per_wen   & per_en;
wire         reg_read  = ~|per_we & per_en;
 
 
// Read/Write vectors
// Read/Write vectors
wire [511:0] reg_wr    = reg_dec & {512{reg_write}};
wire [511:0] reg_wr    = reg_dec & {512{reg_write}};
wire [511:0] reg_rd    = reg_dec & {512{reg_read}};
wire [511:0] reg_rd    = reg_dec & {512{reg_read}};
 
 
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                          cntrl4_rd;
                          cntrl4_rd;
 
 
 
 
endmodule // template_periph_16b
endmodule // template_periph_16b
 
 
`ifdef OMSP_NO_INCLUDE
 
`else
 
`include "openMSP430_undefines.v"
 
`endif
 
 
 
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