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Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 106 $
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// $Rev: 103 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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module template_periph_16b (
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module template_periph_16b (
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// OUTPUTs
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// OUTPUTs
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| Line 50... |
Line 50... |
mclk, // Main system clock
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mclk, // Main system clock
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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per_we, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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puc // Main system reset
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puc_rst // Main system reset
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output [15:0] per_dout; // Peripheral data output
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output [15:0] per_dout; // Peripheral data output
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// INPUTs
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// INPUTs
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//=========
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//=========
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input mclk; // Main system clock
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input mclk; // Main system clock
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input [7:0] per_addr; // Peripheral address
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input [13:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input per_en; // Peripheral enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input puc; // Main system reset
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input puc_rst; // Main system reset
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//=============================================================================
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//=============================================================================
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// 1) PARAMETER DECLARATION
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// 1) PARAMETER DECLARATION
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//=============================================================================
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//=============================================================================
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// Register addresses
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// Register base address (must be aligned to decoder bit width)
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parameter CNTRL1 = 9'h190;
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parameter [14:0] BASE_ADDR = 15'h0190;
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parameter CNTRL2 = 9'h192;
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parameter CNTRL3 = 9'h194;
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parameter CNTRL4 = 9'h196;
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// Decoder bit width (defines how many bits are considered for address decoding)
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parameter DEC_WD = 3;
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// Register addresses offset
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parameter [DEC_WD-1:0] CNTRL1 = 'h0,
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CNTRL2 = 'h2,
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CNTRL3 = 'h4,
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CNTRL4 = 'h6;
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// Register one-hot decoder utilities
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parameter DEC_SZ = 2**DEC_WD;
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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// Register one-hot decoder
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// Register one-hot decoder
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parameter CNTRL1_D = (512'h1 << CNTRL1);
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parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1),
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parameter CNTRL2_D = (512'h1 << CNTRL2);
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CNTRL2_D = (BASE_REG << CNTRL2),
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parameter CNTRL3_D = (512'h1 << CNTRL3);
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CNTRL3_D = (BASE_REG << CNTRL3),
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parameter CNTRL4_D = (512'h1 << CNTRL4);
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CNTRL4_D = (BASE_REG << CNTRL4);
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//============================================================================
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//============================================================================
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// 2) REGISTER DECODER
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// 2) REGISTER DECODER
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//============================================================================
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//============================================================================
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// Local register selection
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wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
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// Register local address
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wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0};
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// Register address decode
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// Register address decode
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reg [511:0] reg_dec;
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wire [DEC_SZ-1:0] reg_dec = (CNTRL1_D & {DEC_SZ{(reg_addr == CNTRL1 )}}) |
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always @(per_addr)
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(CNTRL2_D & {DEC_SZ{(reg_addr == CNTRL2 )}}) |
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case ({per_addr,1'b0})
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(CNTRL3_D & {DEC_SZ{(reg_addr == CNTRL3 )}}) |
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CNTRL1 : reg_dec = CNTRL1_D;
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(CNTRL4_D & {DEC_SZ{(reg_addr == CNTRL4 )}});
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CNTRL2 : reg_dec = CNTRL2_D;
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CNTRL3 : reg_dec = CNTRL3_D;
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CNTRL4 : reg_dec = CNTRL4_D;
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default: reg_dec = {512{1'b0}};
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endcase
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// Read/Write probes
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// Read/Write probes
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wire reg_write = |per_we & per_en;
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wire reg_write = |per_we & reg_sel;
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wire reg_read = ~|per_we & per_en;
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wire reg_read = ~|per_we & reg_sel;
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// Read/Write vectors
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// Read/Write vectors
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wire [511:0] reg_wr = reg_dec & {512{reg_write}};
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wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
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wire [511:0] reg_rd = reg_dec & {512{reg_read}};
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wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
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//============================================================================
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//============================================================================
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// 3) REGISTERS
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// 3) REGISTERS
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//============================================================================
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//============================================================================
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| Line 119... |
Line 129... |
//-----------------
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//-----------------
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reg [15:0] cntrl1;
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reg [15:0] cntrl1;
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wire cntrl1_wr = reg_wr[CNTRL1];
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wire cntrl1_wr = reg_wr[CNTRL1];
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) cntrl1 <= 16'h0000;
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if (puc_rst) cntrl1 <= 16'h0000;
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else if (cntrl1_wr) cntrl1 <= per_din;
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else if (cntrl1_wr) cntrl1 <= per_din;
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// CNTRL2 Register
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// CNTRL2 Register
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//-----------------
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//-----------------
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reg [15:0] cntrl2;
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reg [15:0] cntrl2;
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wire cntrl2_wr = reg_wr[CNTRL2];
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wire cntrl2_wr = reg_wr[CNTRL2];
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) cntrl2 <= 16'h0000;
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if (puc_rst) cntrl2 <= 16'h0000;
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else if (cntrl2_wr) cntrl2 <= per_din;
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else if (cntrl2_wr) cntrl2 <= per_din;
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// CNTRL3 Register
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// CNTRL3 Register
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//-----------------
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//-----------------
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reg [15:0] cntrl3;
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reg [15:0] cntrl3;
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wire cntrl3_wr = reg_wr[CNTRL3];
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wire cntrl3_wr = reg_wr[CNTRL3];
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) cntrl3 <= 16'h0000;
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if (puc_rst) cntrl3 <= 16'h0000;
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else if (cntrl3_wr) cntrl3 <= per_din;
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else if (cntrl3_wr) cntrl3 <= per_din;
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// CNTRL4 Register
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// CNTRL4 Register
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//-----------------
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//-----------------
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reg [15:0] cntrl4;
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reg [15:0] cntrl4;
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wire cntrl4_wr = reg_wr[CNTRL4];
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wire cntrl4_wr = reg_wr[CNTRL4];
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) cntrl4 <= 16'h0000;
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if (puc_rst) cntrl4 <= 16'h0000;
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else if (cntrl4_wr) cntrl4 <= per_din;
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else if (cntrl4_wr) cntrl4 <= per_din;
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//============================================================================
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//============================================================================
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// 4) DATA OUTPUT GENERATION
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// 4) DATA OUTPUT GENERATION
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