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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [periph/] [template_periph_8b.v] - Diff between revs 107 and 111

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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 106 $
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
 
 
module  template_periph_8b (
module  template_periph_8b (
 
 
// OUTPUTs
// OUTPUTs
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    mclk,                           // Main system clock
    mclk,                           // Main system clock
    per_addr,                       // Peripheral address
    per_addr,                       // Peripheral address
    per_din,                        // Peripheral data input
    per_din,                        // Peripheral data input
    per_en,                         // Peripheral enable (high active)
    per_en,                         // Peripheral enable (high active)
    per_we,                         // Peripheral write enable (high active)
    per_we,                         // Peripheral write enable (high active)
    puc                             // Main system reset
    puc_rst                         // Main system reset
);
);
 
 
// OUTPUTs
// OUTPUTs
//=========
//=========
output      [15:0] per_dout;        // Peripheral data output
output      [15:0] per_dout;        // Peripheral data output
 
 
// INPUTs
// INPUTs
//=========
//=========
input              mclk;            // Main system clock
input              mclk;            // Main system clock
input        [7:0] per_addr;        // Peripheral address
input       [13:0] per_addr;        // Peripheral address
input       [15:0] per_din;         // Peripheral data input
input       [15:0] per_din;         // Peripheral data input
input              per_en;          // Peripheral enable (high active)
input              per_en;          // Peripheral enable (high active)
input        [1:0] per_we;          // Peripheral write enable (high active)
input        [1:0] per_we;          // Peripheral write enable (high active)
input              puc;             // Main system reset
input              puc_rst;         // Main system reset
 
 
 
 
//=============================================================================
//=============================================================================
// 1)  PARAMETER DECLARATION
// 1)  PARAMETER DECLARATION
//=============================================================================
//=============================================================================
 
 
// Register addresses
// Register base address (must be aligned to decoder bit width)
parameter          CNTRL1    = 9'h090;
parameter       [14:0] BASE_ADDR   = 15'h0090;
parameter          CNTRL2    = 9'h091;
 
parameter          CNTRL3    = 9'h092;
 
parameter          CNTRL4    = 9'h093;
 
 
 
 
// Decoder bit width (defines how many bits are considered for address decoding)
 
parameter              DEC_WD      =  2;
 
 
 
// Register addresses offset
 
parameter [DEC_WD-1:0] CNTRL1      =  'h0,
 
                       CNTRL2      =  'h1,
 
                       CNTRL3      =  'h2,
 
                       CNTRL4      =  'h3;
 
 
 
 
 
// Register one-hot decoder utilities
 
parameter              DEC_SZ      =  2**DEC_WD;
 
parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
 
 
// Register one-hot decoder
// Register one-hot decoder
parameter          CNTRL1_D  = (256'h1 << (CNTRL1 /2));
parameter [DEC_SZ-1:0] CNTRL1_D  = (BASE_REG << CNTRL1),
parameter          CNTRL2_D  = (256'h1 << (CNTRL2 /2));
                       CNTRL2_D  = (BASE_REG << CNTRL2),
parameter          CNTRL3_D  = (256'h1 << (CNTRL3 /2));
                       CNTRL3_D  = (BASE_REG << CNTRL3),
parameter          CNTRL4_D  = (256'h1 << (CNTRL4 /2));
                       CNTRL4_D  = (BASE_REG << CNTRL4);
 
 
 
 
//============================================================================
//============================================================================
// 2)  REGISTER DECODER
// 2)  REGISTER DECODER
//============================================================================
//============================================================================
 
 
 
// Local register selection
 
wire              reg_sel      =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
 
 
 
// Register local address
 
wire [DEC_WD-1:0] reg_addr     =  {1'b0, per_addr[DEC_WD-2:0]};
 
 
// Register address decode
// Register address decode
reg  [255:0]  reg_dec;
wire [DEC_SZ-1:0] reg_dec      = (CNTRL1_D  &  {DEC_SZ{(reg_addr==(CNTRL1 >>1))}}) |
always @(per_addr)
                                 (CNTRL2_D  &  {DEC_SZ{(reg_addr==(CNTRL2 >>1))}}) |
  case (per_addr)
                                 (CNTRL3_D  &  {DEC_SZ{(reg_addr==(CNTRL3 >>1))}}) |
    (CNTRL1 /2):   reg_dec   = CNTRL1_D;
                                 (CNTRL4_D  &  {DEC_SZ{(reg_addr==(CNTRL4 >>1))}});
    (CNTRL2 /2):   reg_dec   = CNTRL2_D;
 
    (CNTRL3 /2):   reg_dec   = CNTRL3_D;
 
    (CNTRL4 /2):   reg_dec   = CNTRL4_D;
 
    default    :   reg_dec   = {256{1'b0}};
 
  endcase
 
 
 
// Read/Write probes
// Read/Write probes
wire         reg_lo_write =  per_we[0] & per_en;
wire              reg_lo_write =  per_we[0] & reg_sel;
wire         reg_hi_write =  per_we[1] & per_en;
wire              reg_hi_write =  per_we[1] & reg_sel;
wire         reg_read     = ~|per_we   & per_en;
wire              reg_read     = ~|per_we   & reg_sel;
 
 
// Read/Write vectors
// Read/Write vectors
wire [255:0] reg_hi_wr    = reg_dec & {256{reg_hi_write}};
wire [DEC_SZ-1:0] reg_hi_wr    = reg_dec & {DEC_SZ{reg_hi_write}};
wire [255:0] reg_lo_wr    = reg_dec & {256{reg_lo_write}};
wire [DEC_SZ-1:0] reg_lo_wr    = reg_dec & {DEC_SZ{reg_lo_write}};
wire [255:0] reg_rd       = reg_dec & {256{reg_read}};
wire [DEC_SZ-1:0] reg_rd       = reg_dec & {DEC_SZ{reg_read}};
 
 
 
 
//============================================================================
//============================================================================
// 3) REGISTERS
// 3) REGISTERS
//============================================================================
//============================================================================
 
 
// CNTRL1 Register
// CNTRL1 Register
//-----------------
//-----------------
reg  [7:0] cntrl1;
reg  [7:0] cntrl1;
 
 
wire       cntrl1_wr  = CNTRL1[0] ? reg_hi_wr[CNTRL1/2] : reg_lo_wr[CNTRL1/2];
wire       cntrl1_wr  = CNTRL1[0] ? reg_hi_wr[CNTRL1] : reg_lo_wr[CNTRL1];
wire [7:0] cntrl1_nxt = CNTRL1[0] ? per_din[15:8]       : per_din[7:0];
wire [7:0] cntrl1_nxt = CNTRL1[0] ? per_din[15:8]       : per_din[7:0];
 
 
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc_rst)
  if (puc)            cntrl1 <=  8'h00;
  if (puc_rst)        cntrl1 <=  8'h00;
  else if (cntrl1_wr) cntrl1 <=  cntrl1_nxt;
  else if (cntrl1_wr) cntrl1 <=  cntrl1_nxt;
 
 
 
 
// CNTRL2 Register
// CNTRL2 Register
//-----------------
//-----------------
reg  [7:0] cntrl2;
reg  [7:0] cntrl2;
 
 
wire       cntrl2_wr  = CNTRL2[0] ? reg_hi_wr[CNTRL2/2] : reg_lo_wr[CNTRL2/2];
wire       cntrl2_wr  = CNTRL2[0] ? reg_hi_wr[CNTRL2] : reg_lo_wr[CNTRL2];
wire [7:0] cntrl2_nxt = CNTRL2[0] ? per_din[15:8]       : per_din[7:0];
wire [7:0] cntrl2_nxt = CNTRL2[0] ? per_din[15:8]       : per_din[7:0];
 
 
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc_rst)
  if (puc)            cntrl2 <=  8'h00;
  if (puc_rst)        cntrl2 <=  8'h00;
  else if (cntrl2_wr) cntrl2 <=  cntrl2_nxt;
  else if (cntrl2_wr) cntrl2 <=  cntrl2_nxt;
 
 
 
 
// CNTRL3 Register
// CNTRL3 Register
//-----------------
//-----------------
reg  [7:0] cntrl3;
reg  [7:0] cntrl3;
 
 
wire       cntrl3_wr  = CNTRL3[0] ? reg_hi_wr[CNTRL3/2] : reg_lo_wr[CNTRL3/2];
wire       cntrl3_wr  = CNTRL3[0] ? reg_hi_wr[CNTRL3] : reg_lo_wr[CNTRL3];
wire [7:0] cntrl3_nxt = CNTRL3[0] ? per_din[15:8]       : per_din[7:0];
wire [7:0] cntrl3_nxt = CNTRL3[0] ? per_din[15:8]       : per_din[7:0];
 
 
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc_rst)
  if (puc)            cntrl3 <=  8'h00;
  if (puc_rst)        cntrl3 <=  8'h00;
  else if (cntrl3_wr) cntrl3 <=  cntrl3_nxt;
  else if (cntrl3_wr) cntrl3 <=  cntrl3_nxt;
 
 
 
 
// CNTRL4 Register
// CNTRL4 Register
//-----------------
//-----------------
reg  [7:0] cntrl4;
reg  [7:0] cntrl4;
 
 
wire       cntrl4_wr  = CNTRL4[0] ? reg_hi_wr[CNTRL4/2] : reg_lo_wr[CNTRL4/2];
wire       cntrl4_wr  = CNTRL4[0] ? reg_hi_wr[CNTRL4] : reg_lo_wr[CNTRL4];
wire [7:0] cntrl4_nxt = CNTRL4[0] ? per_din[15:8]       : per_din[7:0];
wire [7:0] cntrl4_nxt = CNTRL4[0] ? per_din[15:8]       : per_din[7:0];
 
 
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc_rst)
  if (puc)            cntrl4 <=  8'h00;
  if (puc_rst)        cntrl4 <=  8'h00;
  else if (cntrl4_wr) cntrl4 <=  cntrl4_nxt;
  else if (cntrl4_wr) cntrl4 <=  cntrl4_nxt;
 
 
 
 
 
 
//============================================================================
//============================================================================
// 4) DATA OUTPUT GENERATION
// 4) DATA OUTPUT GENERATION
//============================================================================
//============================================================================
 
 
// Data output mux
// Data output mux
wire [15:0] cntrl1_rd   = {8'h00, (cntrl1  & {8{reg_rd[CNTRL1/2]}})}  << (8 & {4{CNTRL1[0]}});
wire [15:0] cntrl1_rd   = {8'h00, (cntrl1  & {8{reg_rd[CNTRL1]}})}  << (8 & {4{CNTRL1[0]}});
wire [15:0] cntrl2_rd   = {8'h00, (cntrl2  & {8{reg_rd[CNTRL2/2]}})}  << (8 & {4{CNTRL2[0]}});
wire [15:0] cntrl2_rd   = {8'h00, (cntrl2  & {8{reg_rd[CNTRL2]}})}  << (8 & {4{CNTRL2[0]}});
wire [15:0] cntrl3_rd   = {8'h00, (cntrl3  & {8{reg_rd[CNTRL3/2]}})}  << (8 & {4{CNTRL3[0]}});
wire [15:0] cntrl3_rd   = {8'h00, (cntrl3  & {8{reg_rd[CNTRL3]}})}  << (8 & {4{CNTRL3[0]}});
wire [15:0] cntrl4_rd   = {8'h00, (cntrl4  & {8{reg_rd[CNTRL4/2]}})}  << (8 & {4{CNTRL4[0]}});
wire [15:0] cntrl4_rd   = {8'h00, (cntrl4  & {8{reg_rd[CNTRL4]}})}  << (8 & {4{CNTRL4[0]}});
 
 
wire [15:0] per_dout  =  cntrl1_rd  |
wire [15:0] per_dout  =  cntrl1_rd  |
                         cntrl2_rd  |
                         cntrl2_rd  |
                         cntrl3_rd  |
                         cntrl3_rd  |
                         cntrl4_rd;
                         cntrl4_rd;

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