URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [periph/] [template_periph_8b.v] - Diff between revs 111 and 136

Rev 111	Rev 136
Line 1...	Line 1...
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`// Copyright (C) 2009 Authors`	`// Copyright (C) 2009 , Olivier Girard`
`//`	`//`
`// Redistribution and use in source and binary forms, with or without`	`// Redistribution and use in source and binary forms, with or without`
`// modification, are permitted provided that the following conditions`	`// modification, are permitted provided that the following conditions`
`// are met:`	`// are met:`
`// * Redistributions of source code must retain the above copyright`	`// * Redistributions of source code must retain the above copyright`
Line 85...	Line 85...
`CNTRL3 = 'h2,`	`CNTRL3 = 'h2,`
`CNTRL4 = 'h3;`	`CNTRL4 = 'h3;`


`// Register one-hot decoder utilities`	`// Register one-hot decoder utilities`
`parameter DEC_SZ = 2**DEC_WD;`	`parameter DEC_SZ = (1 << DEC_WD);`
`parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};`	`parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};`

`// Register one-hot decoder`	`// Register one-hot decoder`
`parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1),`	`parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1),`
`CNTRL2_D = (BASE_REG << CNTRL2),`	`CNTRL2_D = (BASE_REG << CNTRL2),`