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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [smartgen/] [dmem_128B.v] - Diff between revs 80 and 81

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Rev 80 Rev 81
Line 12... Line 12...
 
 
    wire VCC, GND;
    wire VCC, GND;
 
 
    VCC VCC_1_net(.Y(VCC));
    VCC VCC_1_net(.Y(VCC));
    GND GND_1_net(.Y(GND));
    GND GND_1_net(.Y(GND));
    RAM4K9 #( .MEMORYFILE() )
    RAM4K9 dmem_128B_R0C0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
        dmem_128B_R0C0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
 
        GND), .ADDRA8(GND), .ADDRA7(GND), .ADDRA6(WADDR[6]),
        GND), .ADDRA8(GND), .ADDRA7(GND), .ADDRA6(WADDR[6]),
        .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(WADDR[3]),
        .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(WADDR[3]),
        .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(WADDR[0]),
        .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(WADDR[0]),
        .ADDRB11(GND), .ADDRB10(GND), .ADDRB9(GND), .ADDRB8(GND),
        .ADDRB11(GND), .ADDRB10(GND), .ADDRB9(GND), .ADDRB8(GND),
        .ADDRB7(GND), .ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]),
        .ADDRB7(GND), .ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]),

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