URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [sim/] [rtl_sim/] [bin/] [rtlsim.sh] - Diff between revs 138 and 212

Rev 138	Rev 212
Line 80...	Line 80...
`iverilog -o simv -c $3 -D NODUMP`	`iverilog -o simv -c $3 -D NODUMP`
`else`	`else`
`iverilog -o simv -c $3`	`iverilog -o simv -c $3`
`fi`	`fi`

if [ `uname -o` = "Cygwin" ]	`if [[ $(uname -s) == CYGWIN* ]];`
`then`	`then`
`vvp.exe ./simv`	`vvp.exe ./simv`
`else`	`else`
`./simv`	`./simv`
`fi`	`fi`
Line 103...	Line 103...
`vargs="$vargs +define+VXL +define+CVER" ;;`	`vargs="$vargs +define+VXL +define+CVER" ;;`
`verilog* )`	`verilog* )`
`vargs="$vargs +define+VXL" ;;`	`vargs="$vargs +define+VXL" ;;`
`ncverilog* )`	`ncverilog* )`
`rm -rf INCA_libs`	`rm -rf INCA_libs`
`vargs="$vargs +access+r +nclicq +ncinput+../bin/cov_ncverilog.tcl -covdut openMSP430 -covfile ../bin/cov_ncverilog.ccf -coverage all +define+TRN_FILE" ;;`	`#vargs="$vargs +access+r +nclicq +ncinput+../bin/cov_ncverilog.tcl -covdut openMSP430 -covfile ../bin/cov_ncverilog.ccf -coverage all +define+TRN_FILE" ;;`
	`vargs="$vargs +access+r +nclicq +define+TRN_FILE" ;;`
`vcs* )`	`vcs* )`
`rm -rf csrc simv*`	`rm -rf csrc simv*`
`vargs="$vargs -R -debug_pp +vcs+lic+wait +v2k +define+VPD_FILE" ;;`	`vargs="$vargs -R -debug_pp +vcs+lic+wait +v2k +define+VPD_FILE" ;;`
`vsim* )`	`vsim* )`
`# Modelsim`	`# Modelsim`