| Line 31... |
Line 31... |
// $Rev: 71 $
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// $Rev: 71 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2010-03-07 21:14:33 +0100 (Sun, 07 Mar 2010) $
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// $LastChangedDate: 2010-03-07 21:14:33 +0100 (Sun, 07 Mar 2010) $
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//=============================================================================
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//=============================================================================
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//=============================================================================
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// Testbench related
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//=============================================================================
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+incdir+../../../bench/verilog/
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../../../bench/verilog/tb_openMSP430_fpga.v
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../../../bench/verilog/msp_debug.v
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../../../bench/verilog/DAC121S101.v
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//=============================================================================
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//=============================================================================
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// Actel library
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// Actel library
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//=============================================================================
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//=============================================================================
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+libext+.v
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+libext+.v
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| Line 71... |
Line 82... |
../../../rtl/verilog/openmsp430/omsp_watchdog.v
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../../../rtl/verilog/openmsp430/omsp_watchdog.v
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../../../rtl/verilog/openmsp430/omsp_multiplier.v
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../../../rtl/verilog/openmsp430/omsp_multiplier.v
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../../../rtl/verilog/openmsp430/periph/omsp_gpio.v
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../../../rtl/verilog/openmsp430/periph/omsp_gpio.v
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../../../rtl/verilog/openmsp430/periph/omsp_timerA.v
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../../../rtl/verilog/openmsp430/periph/omsp_timerA.v
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//=============================================================================
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// Testbench related
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//=============================================================================
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+incdir+../../../bench/verilog/
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../../../bench/verilog/tb_openMSP430_fpga.v
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../../../bench/verilog/msp_debug.v
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../../../bench/verilog/DAC121S101.v
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No newline at end of file
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No newline at end of file
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