URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [sim/] [rtl_sim/] [src/] [submit.f] - Diff between revs 105 and 107

Rev 105	Rev 107
Line 66...	Line 66...
`//=============================================================================`	`//=============================================================================`
`// openMSP430`	`// openMSP430`
`//=============================================================================`	`//=============================================================================`

`+incdir+../../../rtl/verilog/openmsp430/`	`+incdir+../../../rtl/verilog/openmsp430/`
	`+incdir+../../../rtl/verilog/openmsp430/periph`
`../../../rtl/verilog/openmsp430/openMSP430.v`	`../../../rtl/verilog/openmsp430/openMSP430.v`
`../../../rtl/verilog/openmsp430/omsp_frontend.v`	`../../../rtl/verilog/openmsp430/omsp_frontend.v`
`../../../rtl/verilog/openmsp430/omsp_execution_unit.v`	`../../../rtl/verilog/openmsp430/omsp_execution_unit.v`
`../../../rtl/verilog/openmsp430/omsp_register_file.v`	`../../../rtl/verilog/openmsp430/omsp_register_file.v`
`../../../rtl/verilog/openmsp430/omsp_alu.v`	`../../../rtl/verilog/openmsp430/omsp_alu.v`