URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [software/] [spacewar/] [hardware.c] - Diff between revs 80 and 84

Rev 80	Rev 84
Line 33...	Line 33...

`P1OUT = 0x04; // TLV5618A CS high`	`P1OUT = 0x04; // TLV5618A CS high`
`P1DIR \|= 0x01+0x04; // P1.0=LED, P1.2=TLV5618A_cs`	`P1DIR \|= 0x01+0x04; // P1.0=LED, P1.2=TLV5618A_cs`
`P1SEL = 0x08; // P1.3 = VREF`	`P1SEL = 0x08; // P1.3 = VREF`

	`//BCSCTL2 = 0x00; // SMCLK divider = 1`
	`//BCSCTL2 = 0x02; // SMCLK divider = 2`
	`//BCSCTL2 = 0x04; // SMCLK divider = 4`
	`BCSCTL2 = 0x06; // SMCLK divider = 8`
`CCTL0 = CCIE; // CCR0 interrupt enabled`	`CCTL0 = CCIE; // CCR0 interrupt enabled`
`CCR0 = 23500;`	`CCR0 = 23500;`
`//CCR0 = 500;`
`TACTL = TASSEL_2 + MC_1; // SMCLK, upmode`	`TACTL = TASSEL_2 + MC_1; // SMCLK, upmode`
`_BIS_SR(GIE); // enable interrupts`	`_BIS_SR(GIE); // enable interrupts`

`// USICTL0 \|= USIPE7+USIPE6+USIPE5+USIMST+USIOE; // Port, SPI master`	`// USICTL0 \|= USIPE7+USIPE6+USIPE5+USIMST+USIOE; // Port, SPI master`
`// USICKCTL = USIDIV_0+USISSEL_2+USICKPL; // divide by 1 SMCLK, inactive high`	`// USICKCTL = USIDIV_0+USISSEL_2+USICKPL; // divide by 1 SMCLK, inactive high`