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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel/] [design_files.v] - Diff between revs 111 and 136

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Rev 111 Rev 136
Line 49... Line 49...
`include "../../../rtl/verilog/openmsp430/openMSP430.v"
`include "../../../rtl/verilog/openmsp430/openMSP430.v"
`include "../../../rtl/verilog/openmsp430/omsp_frontend.v"
`include "../../../rtl/verilog/openmsp430/omsp_frontend.v"
`include "../../../rtl/verilog/openmsp430/omsp_execution_unit.v"
`include "../../../rtl/verilog/openmsp430/omsp_execution_unit.v"
`include "../../../rtl/verilog/openmsp430/omsp_register_file.v"
`include "../../../rtl/verilog/openmsp430/omsp_register_file.v"
`include "../../../rtl/verilog/openmsp430/omsp_alu.v"
`include "../../../rtl/verilog/openmsp430/omsp_alu.v"
`include "../../../rtl/verilog/openmsp430/omsp_mem_backbone.v"
 
`include "../../../rtl/verilog/openmsp430/omsp_clock_module.v"
 
`include "../../../rtl/verilog/openmsp430/omsp_sfr.v"
`include "../../../rtl/verilog/openmsp430/omsp_sfr.v"
 
`include "../../../rtl/verilog/openmsp430/omsp_clock_module.v"
 
`include "../../../rtl/verilog/openmsp430/omsp_mem_backbone.v"
`include "../../../rtl/verilog/openmsp430/omsp_watchdog.v"
`include "../../../rtl/verilog/openmsp430/omsp_watchdog.v"
`include "../../../rtl/verilog/openmsp430/omsp_dbg.v"
`include "../../../rtl/verilog/openmsp430/omsp_dbg.v"
`include "../../../rtl/verilog/openmsp430/omsp_dbg_uart.v"
`include "../../../rtl/verilog/openmsp430/omsp_dbg_uart.v"
`include "../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v"
`include "../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v"
`include "../../../rtl/verilog/openmsp430/omsp_multiplier.v"
`include "../../../rtl/verilog/openmsp430/omsp_multiplier.v"
 
`include "../../../rtl/verilog/openmsp430/omsp_sync_reset.v"
`include "../../../rtl/verilog/openmsp430/omsp_sync_cell.v"
`include "../../../rtl/verilog/openmsp430/omsp_sync_cell.v"
 
`include "../../../rtl/verilog/openmsp430/omsp_scan_mux.v"
 
`include "../../../rtl/verilog/openmsp430/omsp_and_gate.v"
 
`include "../../../rtl/verilog/openmsp430/omsp_wakeup_cell.v"
 
`include "../../../rtl/verilog/openmsp430/omsp_clock_gate.v"
 
`include "../../../rtl/verilog/openmsp430/omsp_clock_mux.v"
`include "../../../rtl/verilog/openmsp430/periph/omsp_gpio.v"
`include "../../../rtl/verilog/openmsp430/periph/omsp_gpio.v"
`include "../../../rtl/verilog/openmsp430/periph/omsp_timerA.v"
`include "../../../rtl/verilog/openmsp430/periph/omsp_timerA.v"
 
 
 
 
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