URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel/] [design_files.v] - Diff between revs 136 and 155

Rev 136	Rev 155
Line 55...	Line 55...
`include "../../../rtl/verilog/openmsp430/omsp_clock_module.v"	`include "../../../rtl/verilog/openmsp430/omsp_clock_module.v"
`include "../../../rtl/verilog/openmsp430/omsp_mem_backbone.v"	`include "../../../rtl/verilog/openmsp430/omsp_mem_backbone.v"
`include "../../../rtl/verilog/openmsp430/omsp_watchdog.v"	`include "../../../rtl/verilog/openmsp430/omsp_watchdog.v"
`include "../../../rtl/verilog/openmsp430/omsp_dbg.v"	`include "../../../rtl/verilog/openmsp430/omsp_dbg.v"
`include "../../../rtl/verilog/openmsp430/omsp_dbg_uart.v"	`include "../../../rtl/verilog/openmsp430/omsp_dbg_uart.v"
	`include "../../../rtl/verilog/openmsp430/omsp_dbg_i2c.v"
`include "../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v"	`include "../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v"
`include "../../../rtl/verilog/openmsp430/omsp_multiplier.v"	`include "../../../rtl/verilog/openmsp430/omsp_multiplier.v"
`include "../../../rtl/verilog/openmsp430/omsp_sync_reset.v"	`include "../../../rtl/verilog/openmsp430/omsp_sync_reset.v"
`include "../../../rtl/verilog/openmsp430/omsp_sync_cell.v"	`include "../../../rtl/verilog/openmsp430/omsp_sync_cell.v"
`include "../../../rtl/verilog/openmsp430/omsp_scan_mux.v"	`include "../../../rtl/verilog/openmsp430/omsp_scan_mux.v"