URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel/] [design_files.v] - Diff between revs 80 and 82

Rev 80	Rev 82
Line 56...	Line 56...
`include "../../../rtl/verilog/openmsp430/omsp_sfr.v"	`include "../../../rtl/verilog/openmsp430/omsp_sfr.v"
`include "../../../rtl/verilog/openmsp430/omsp_watchdog.v"	`include "../../../rtl/verilog/openmsp430/omsp_watchdog.v"
`include "../../../rtl/verilog/openmsp430/omsp_dbg.v"	`include "../../../rtl/verilog/openmsp430/omsp_dbg.v"
`include "../../../rtl/verilog/openmsp430/omsp_dbg_uart.v"	`include "../../../rtl/verilog/openmsp430/omsp_dbg_uart.v"
`include "../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v"	`include "../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v"
	`include "../../../rtl/verilog/openmsp430/omsp_multiplier.v"
`include "../../../rtl/verilog/openmsp430/periph/omsp_gpio.v"	`include "../../../rtl/verilog/openmsp430/periph/omsp_gpio.v"
`include "../../../rtl/verilog/openmsp430/periph/omsp_timerA.v"	`include "../../../rtl/verilog/openmsp430/periph/omsp_timerA.v"


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