URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel/] [prepare_implementation.tcl] - Diff between revs 107 and 136

Rev 107	Rev 136
Line 53...	Line 53...

`# RTL Top Level module`	`# RTL Top Level module`
`set designTop "openMSP430_fpga"`	`set designTop "openMSP430_fpga"`

`# RTL include files`	`# RTL include files`
`set rtlIncludeFiles "../../../rtl/verilog/openmsp430/timescale.v \`	`set rtlIncludeFiles "../../../rtl/verilog/openmsp430/openMSP430_defines.v \`
`../../../rtl/verilog/openmsp430/openMSP430_defines.v \`
`../../../rtl/verilog/openmsp430/openMSP430_undefines.v \`	`../../../rtl/verilog/openmsp430/openMSP430_undefines.v \`
`../../../rtl/verilog/openmsp430/periph/omsp_timerA_defines.v \`	`../../../rtl/verilog/openmsp430/periph/omsp_timerA_defines.v \`
`../../../rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v"`	`../../../rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v"`

`###############################################################################`	`###############################################################################`