| Line 86... |
Line 86... |
lut_ram_dout_i, // LUT-RAM data output
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lut_ram_dout_i, // LUT-RAM data output
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`endif
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`endif
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vid_ram_dout_i // Video-RAM data output
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vid_ram_dout_i // Video-RAM data output
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);
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);
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|
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// PARAMETERs
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//============
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|
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parameter [14:0] BASE_ADDR = 15'h0200; // Register base address
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// - 7 LSBs must stay cleared: 0x0080, 0x0100,
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// 0x0180, 0x0200,
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// 0x0280, ...
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output irq_gfx_o; // Graphic Controller interrupt
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output irq_gfx_o; // Graphic Controller interrupt
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output lt24_cs_n_o; // LT24 Chip select (Active low)
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output lt24_cs_n_o; // LT24 Chip select (Active low)
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| Line 191... |
Line 198... |
wire refresh_active;
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wire refresh_active;
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wire [15:0] refresh_data;
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wire [15:0] refresh_data;
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wire refresh_data_ready;
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wire refresh_data_ready;
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wire refresh_data_request;
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wire refresh_data_request;
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wire [`APIX_MSB:0] refresh_frame_addr;
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wire [`APIX_MSB:0] refresh_frame_addr;
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wire [1:0] refresh_lut_select;
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wire [2:0] hw_lut_palette_sel;
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wire [3:0] hw_lut_bgcolor;
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wire [3:0] hw_lut_fgcolor;
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wire sw_lut_enable;
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wire sw_lut_bank_select;
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wire gpu_cmd_done_evt;
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wire gpu_cmd_done_evt;
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wire gpu_cmd_error_evt;
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wire gpu_cmd_error_evt;
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wire gpu_dma_busy;
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wire gpu_dma_busy;
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wire gpu_get_data;
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wire gpu_get_data;
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| Line 206... |
Line 217... |
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//============================================================================
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//============================================================================
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// 2) REGISTERS
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// 2) REGISTERS
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//============================================================================
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//============================================================================
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ogfx_reg ogfx_reg_inst (
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ogfx_reg #(.BASE_ADDR(BASE_ADDR)) ogfx_reg_inst (
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|
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// OUTPUTs
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// OUTPUTs
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.irq_gfx_o ( irq_gfx_o ), // Graphic Controller interrupt
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.irq_gfx_o ( irq_gfx_o ), // Graphic Controller interrupt
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|
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.gpu_data_o ( gpu_data ), // GPU data
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.gpu_data_o ( gpu_data ), // GPU data
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| Line 241... |
Line 252... |
.gfx_mode_o ( gfx_mode ), // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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.gfx_mode_o ( gfx_mode ), // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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.per_dout_o ( per_dout_o ), // Peripheral data output
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.per_dout_o ( per_dout_o ), // Peripheral data output
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.refresh_frame_addr_o ( refresh_frame_addr ), // Refresh frame base address
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.refresh_frame_addr_o ( refresh_frame_addr ), // Refresh frame base address
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.refresh_lut_select_o ( refresh_lut_select ), // Refresh LUT bank selection
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.hw_lut_palette_sel_o ( hw_lut_palette_sel ), // Hardware LUT palette configuration
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.hw_lut_bgcolor_o ( hw_lut_bgcolor ), // Hardware LUT background-color selection
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.hw_lut_fgcolor_o ( hw_lut_fgcolor ), // Hardware LUT foreground-color selection
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.sw_lut_enable_o ( sw_lut_enable ), // Refresh LUT-RAM enable
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.sw_lut_bank_select_o ( sw_lut_bank_select ), // Refresh LUT-RAM bank selection
|
|
|
`ifdef WITH_PROGRAMMABLE_LUT
|
`ifdef WITH_PROGRAMMABLE_LUT
|
.lut_ram_addr_o ( lut_ram_sw_addr ), // LUT-RAM address
|
.lut_ram_addr_o ( lut_ram_sw_addr ), // LUT-RAM address
|
.lut_ram_din_o ( lut_ram_sw_din ), // LUT-RAM data
|
.lut_ram_din_o ( lut_ram_sw_din ), // LUT-RAM data
|
.lut_ram_wen_o ( lut_ram_sw_wen ), // LUT-RAM write strobe (active low)
|
.lut_ram_wen_o ( lut_ram_sw_wen ), // LUT-RAM write strobe (active low)
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| Line 403... |
Line 419... |
.vid_ram_dout_rdy_nxt_i ( vid_ram_refr_dout_rdy_nxt ), // Video-RAM data output ready during next cycle
|
.vid_ram_dout_rdy_nxt_i ( vid_ram_refr_dout_rdy_nxt ), // Video-RAM data output ready during next cycle
|
|
|
.refresh_active_i ( refresh_active ), // Display refresh on going
|
.refresh_active_i ( refresh_active ), // Display refresh on going
|
.refresh_data_request_i ( refresh_data_request ), // Display refresh new data request
|
.refresh_data_request_i ( refresh_data_request ), // Display refresh new data request
|
.refresh_frame_base_addr_i ( refresh_frame_addr ), // Refresh frame base address
|
.refresh_frame_base_addr_i ( refresh_frame_addr ), // Refresh frame base address
|
.refresh_lut_select_i ( refresh_lut_select ) // Refresh LUT bank selection
|
|
|
.hw_lut_palette_sel_i ( hw_lut_palette_sel ), // Hardware LUT palette configuration
|
|
.hw_lut_bgcolor_i ( hw_lut_bgcolor ), // Hardware LUT background-color selection
|
|
.hw_lut_fgcolor_i ( hw_lut_fgcolor ), // Hardware LUT foreground-color selection
|
|
.sw_lut_enable_i ( sw_lut_enable ), // Refresh LUT-RAM enable
|
|
.sw_lut_bank_select_i ( sw_lut_bank_select ) // Refresh LUT-RAM bank selection
|
);
|
);
|
|
|
//============================================================================
|
//============================================================================
|
// 6) ARBITER FOR VIDEO AND LUT MEMORIES
|
// 6) ARBITER FOR VIDEO AND LUT MEMORIES
|
//============================================================================
|
//============================================================================
|
