| Line 50... |
Line 50... |
inst_number, // Instruction number since last system reset
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inst_number, // Instruction number since last system reset
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inst_pc, // Instruction Program counter
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inst_pc, // Instruction Program counter
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inst_short, // Currently executed instruction (short version)
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inst_short, // Currently executed instruction (short version)
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// INPUTs
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// INPUTs
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mclk, // Main system clock
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core_select // Core selection
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puc_rst // Main system reset
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);
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);
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// OUTPUTs
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// OUTPUTs
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//============
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//============
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output [8*32-1:0] e_state; // Execution state
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output [8*32-1:0] e_state; // Execution state
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| Line 66... |
Line 65... |
output [15:0] inst_pc; // Instruction Program counter
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output [15:0] inst_pc; // Instruction Program counter
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output [8*32-1:0] inst_short; // Currently executed instruction (short version)
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output [8*32-1:0] inst_short; // Currently executed instruction (short version)
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// INPUTs
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// INPUTs
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//============
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//============
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input mclk; // Main system clock
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input core_select; // Core selection
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input puc_rst; // Main system reset
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//=============================================================================
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//=============================================================================
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// 1) ASCII FORMATING FUNCTIONS
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// 1) ASCII FORMATING FUNCTIONS
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//=============================================================================
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//=============================================================================
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| Line 110... |
Line 108... |
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//=============================================================================
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//=============================================================================
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// 2) CONNECTIONS TO MSP430 CORE INTERNALS
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// 2) CONNECTIONS TO MSP430 CORE INTERNALS
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//=============================================================================
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//=============================================================================
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wire [2:0] i_state_bin = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.i_state;
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//-------------------------
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wire [3:0] e_state_bin = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.e_state;
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// CPU 0
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//-------------------------
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wire [2:0] omsp0_i_state_bin = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.i_state;
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wire [3:0] omsp0_e_state_bin = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.e_state;
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wire omsp0_decode = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.decode;
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wire [15:0] omsp0_ir = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.ir;
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wire omsp0_irq_detect = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.irq_detect;
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wire [3:0] omsp0_irq_num = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.irq_num;
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wire [15:0] omsp0_pc = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.pc;
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wire omsp0_mclk = tb_openMSP430_fpga.dut.omsp_system_0_inst.mclk;
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wire omsp0_puc_rst = tb_openMSP430_fpga.dut.omsp_system_0_inst.puc_rst;
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//-------------------------
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// CPU 1
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//-------------------------
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wire [2:0] omsp1_i_state_bin = tb_openMSP430_fpga.dut.omsp_system_1_inst.openMSP430_0.frontend_0.i_state;
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wire [3:0] omsp1_e_state_bin = tb_openMSP430_fpga.dut.omsp_system_1_inst.openMSP430_0.frontend_0.e_state;
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wire omsp1_decode = tb_openMSP430_fpga.dut.omsp_system_1_inst.openMSP430_0.frontend_0.decode;
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wire [15:0] omsp1_ir = tb_openMSP430_fpga.dut.omsp_system_1_inst.openMSP430_0.frontend_0.ir;
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wire omsp1_irq_detect = tb_openMSP430_fpga.dut.omsp_system_1_inst.openMSP430_0.frontend_0.irq_detect;
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wire [3:0] omsp1_irq_num = tb_openMSP430_fpga.dut.omsp_system_1_inst.openMSP430_0.frontend_0.irq_num;
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wire [15:0] omsp1_pc = tb_openMSP430_fpga.dut.omsp_system_1_inst.openMSP430_0.frontend_0.pc;
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wire omsp1_mclk = tb_openMSP430_fpga.dut.omsp_system_1_inst.mclk;
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wire omsp1_puc_rst = tb_openMSP430_fpga.dut.omsp_system_1_inst.puc_rst;
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//-------------------------
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// CPU Selection
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//-------------------------
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wire [2:0] i_state_bin = core_select ? omsp1_i_state_bin : omsp0_i_state_bin;
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wire [3:0] e_state_bin = core_select ? omsp1_e_state_bin : omsp0_e_state_bin;
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wire decode = core_select ? omsp1_decode : omsp0_decode;
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wire [15:0] ir = core_select ? omsp1_ir : omsp0_ir;
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wire irq_detect = core_select ? omsp1_irq_detect : omsp0_irq_detect;
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wire [3:0] irq_num = core_select ? omsp1_irq_num : omsp0_irq_num;
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wire [15:0] pc = core_select ? omsp1_pc : omsp0_pc;
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wire decode = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.decode;
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wire mclk = core_select ? omsp1_mclk : omsp0_mclk;
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wire [15:0] ir = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.ir;
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wire puc_rst = core_select ? omsp1_puc_rst : omsp0_puc_rst;
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wire irq_detect = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.irq_detect;
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wire [3:0] irq_num = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.irq_num;
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wire [15:0] pc = tb_openMSP430_fpga.dut.omsp_system_0_inst.openMSP430_0.frontend_0.pc;
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//=============================================================================
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//=============================================================================
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// 3) GENERATE DEBUG SIGNALS
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// 3) GENERATE DEBUG SIGNALS
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//=============================================================================
|
//=============================================================================
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