URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Diff between revs 157 and 162

Rev 157	Rev 162
Line 70...	Line 70...
`wire UART_TXD;`	`wire UART_TXD;`

`// UART`	`// UART`
`wire PMOD1_P1;`	`wire PMOD1_P1;`
`reg PMOD1_P4;`	`reg PMOD1_P4;`
`reg PMOD1_P8;`

`// Core debug signals`	`// Core debug signals`
`wire [8*32-1:0] i_state;`	`wire [8*32-1:0] i_state;`
`wire [8*32-1:0] e_state;`	`wire [8*32-1:0] e_state;`
`wire [31:0] inst_cycle;`	`wire [31:0] inst_cycle;`
Line 154...	Line 153...
`SW3 = 1'b0;`	`SW3 = 1'b0;`
`SW2 = 1'b0;`	`SW2 = 1'b0;`
`SW1 = 1'b0;`	`SW1 = 1'b0;`
`UART_RXD = 1'b1; // UART`	`UART_RXD = 1'b1; // UART`
`PMOD1_P4 = 1'b1;`	`PMOD1_P4 = 1'b1;`
`PMOD1_P8 = 1'b0;`
`end`	`end`

`//`	`//`
`// openMSP430 FPGA Instance`	`// openMSP430 FPGA Instance`
`//----------------------------------`	`//----------------------------------`
Line 316...	Line 314...
`.PMOD1_P1 (PMOD1_P1), // Serial Debug Interface TX`	`.PMOD1_P1 (PMOD1_P1), // Serial Debug Interface TX`
`.PMOD1_P2 (),`	`.PMOD1_P2 (),`
`.PMOD1_P3 (),`	`.PMOD1_P3 (),`
`.PMOD1_P4 (PMOD1_P4), // Serial Debug Interface RX`	`.PMOD1_P4 (PMOD1_P4), // Serial Debug Interface RX`
`.PMOD1_P7 (),`	`.PMOD1_P7 (),`
`.PMOD1_P8 (PMOD1_P8), // Serial Debug Interface enable`	`.PMOD1_P8 (),`
`.PMOD1_P9 (),`	`.PMOD1_P9 (),`
`.PMOD1_P10 (),`	`.PMOD1_P10 (),`

`// Connector J4`	`// Connector J4`
`.PMOD2_P1 (),`	`.PMOD2_P1 (),`