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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Diff between revs 162 and 167

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Rev 162 Rev 167
Line 72... Line 72...
// UART
// UART
wire              PMOD1_P1;
wire              PMOD1_P1;
reg               PMOD1_P4;
reg               PMOD1_P4;
 
 
// Core debug signals
// Core debug signals
wire   [8*32-1:0] i_state;
wire   [8*32-1:0] omsp0_i_state;
wire   [8*32-1:0] e_state;
wire   [8*32-1:0] omsp0_e_state;
wire       [31:0] inst_cycle;
wire       [31:0] omsp0_inst_cycle;
wire   [8*32-1:0] inst_full;
wire   [8*32-1:0] omsp0_inst_full;
wire       [31:0] inst_number;
wire       [31:0] omsp0_inst_number;
wire       [15:0] inst_pc;
wire       [15:0] omsp0_inst_pc;
wire   [8*32-1:0] inst_short;
wire   [8*32-1:0] omsp0_inst_short;
 
 
 
wire   [8*32-1:0] omsp1_i_state;
 
wire   [8*32-1:0] omsp1_e_state;
 
wire       [31:0] omsp1_inst_cycle;
 
wire   [8*32-1:0] omsp1_inst_full;
 
wire       [31:0] omsp1_inst_number;
 
wire       [15:0] omsp1_inst_pc;
 
wire   [8*32-1:0] omsp1_inst_short;
 
 
// Testbench variables
// Testbench variables
integer           i;
integer           i;
integer           error;
integer           error;
reg               stimulus_done;
reg               stimulus_done;
Line 91... Line 99...
//
//
// Include files
// Include files
//------------------------------
//------------------------------
 
 
// CPU & Memory registers
// CPU & Memory registers
`include "registers.v"
`include "registers_omsp0.v"
 
`include "registers_omsp1.v"
 
 
// Verilog stimulus
// Verilog stimulus
`include "stimulus.v"
`include "stimulus.v"
 
 
//
//
Line 106... Line 115...
   begin
   begin
      // Read memory file
      // Read memory file
      #10 $readmemh("./pmem.mem", pmem);
      #10 $readmemh("./pmem.mem", pmem);
 
 
      // Update Xilinx memory banks
      // Update Xilinx memory banks
      for (i=0; i<2048; i=i+1)
      for (i=0; i<8192; i=i+1)
        begin
        begin
           dut.ram_16x2k_pmem.ram_inst.mem[i] = pmem[i];
           dut.ram_16x8k_dp_pmem_shared.ram_dp_inst.mem[i] = pmem[i];
        end
        end
  end
  end
 
 
//
//
// Generate Clock & Reset
// Generate Clock & Reset
Line 332... Line 341...
);
);
 
 
 
 
// Debug utility signals
// Debug utility signals
//----------------------------------------
//----------------------------------------
msp_debug msp_debug_0 (
msp_debug msp_debug_omsp0 (
 
 
// OUTPUTs
// OUTPUTs
    .e_state      (e_state),       // Execution state
    .e_state      (omsp0_e_state),       // Execution state
    .i_state      (i_state),       // Instruction fetch state
    .i_state      (omsp0_i_state),       // Instruction fetch state
    .inst_cycle   (inst_cycle),    // Cycle number within current instruction
    .inst_cycle   (omsp0_inst_cycle),    // Cycle number within current instruction
    .inst_full    (inst_full),     // Currently executed instruction (full version)
    .inst_full    (omsp0_inst_full),     // Currently executed instruction (full version)
    .inst_number  (inst_number),   // Instruction number since last system reset
    .inst_number  (omsp0_inst_number),   // Instruction number since last system reset
    .inst_pc      (inst_pc),       // Instruction Program counter
    .inst_pc      (omsp0_inst_pc),       // Instruction Program counter
    .inst_short   (inst_short),    // Currently executed instruction (short version)
    .inst_short   (omsp0_inst_short),    // Currently executed instruction (short version)
 
 
// INPUTs
// INPUTs
    .mclk         (mclk),          // Main system clock
    .core_select  (0)                    // Core selection
    .puc_rst      (puc_rst)        // Main system reset
);
 
 
 
msp_debug msp_debug_omsp1 (
 
 
 
// OUTPUTs
 
    .e_state      (omsp1_e_state),       // Execution state
 
    .i_state      (omsp1_i_state),       // Instruction fetch state
 
    .inst_cycle   (omsp1_inst_cycle),    // Cycle number within current instruction
 
    .inst_full    (omsp1_inst_full),     // Currently executed instruction (full version)
 
    .inst_number  (omsp1_inst_number),   // Instruction number since last system reset
 
    .inst_pc      (omsp1_inst_pc),       // Instruction Program counter
 
    .inst_short   (omsp1_inst_short),    // Currently executed instruction (short version)
 
 
 
// INPUTs
 
    .core_select  (1)                    // Core selection
);
);
 
 
//
//
// Generate Waveform
// Generate Waveform
//----------------------------------------
//----------------------------------------
Line 383... Line 406...
     $finish;
     $finish;
  end
  end
 
 
initial // Normal end of test
initial // Normal end of test
  begin
  begin
     @(inst_pc===16'hffff)
     @(omsp0_inst_pc===16'hffff)
     $display(" ===============================================");
     $display(" ===============================================");
     if (error!=0)
     if (error!=0)
       begin
       begin
          $display("|               SIMULATION FAILED               |");
          $display("|               SIMULATION FAILED               |");
          $display("|     (some verilog stimulus checks failed)     |");
          $display("|     (some verilog stimulus checks failed)     |");

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