| Line 72... |
Line 72... |
// UART
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// UART
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wire PMOD1_P1;
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wire PMOD1_P1;
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reg PMOD1_P4;
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reg PMOD1_P4;
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// Core debug signals
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// Core debug signals
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wire [8*32-1:0] i_state;
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wire [8*32-1:0] omsp0_i_state;
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wire [8*32-1:0] e_state;
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wire [8*32-1:0] omsp0_e_state;
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wire [31:0] inst_cycle;
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wire [31:0] omsp0_inst_cycle;
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wire [8*32-1:0] inst_full;
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wire [8*32-1:0] omsp0_inst_full;
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wire [31:0] inst_number;
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wire [31:0] omsp0_inst_number;
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wire [15:0] inst_pc;
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wire [15:0] omsp0_inst_pc;
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wire [8*32-1:0] inst_short;
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wire [8*32-1:0] omsp0_inst_short;
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wire [8*32-1:0] omsp1_i_state;
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wire [8*32-1:0] omsp1_e_state;
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wire [31:0] omsp1_inst_cycle;
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wire [8*32-1:0] omsp1_inst_full;
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wire [31:0] omsp1_inst_number;
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wire [15:0] omsp1_inst_pc;
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wire [8*32-1:0] omsp1_inst_short;
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// Testbench variables
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// Testbench variables
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integer i;
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integer i;
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integer error;
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integer error;
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reg stimulus_done;
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reg stimulus_done;
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| Line 91... |
Line 99... |
//
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//
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// Include files
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// Include files
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//------------------------------
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//------------------------------
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// CPU & Memory registers
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// CPU & Memory registers
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`include "registers.v"
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`include "registers_omsp0.v"
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`include "registers_omsp1.v"
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// Verilog stimulus
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// Verilog stimulus
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`include "stimulus.v"
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`include "stimulus.v"
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//
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//
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| Line 106... |
Line 115... |
begin
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begin
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// Read memory file
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// Read memory file
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#10 $readmemh("./pmem.mem", pmem);
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#10 $readmemh("./pmem.mem", pmem);
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// Update Xilinx memory banks
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// Update Xilinx memory banks
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for (i=0; i<2048; i=i+1)
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for (i=0; i<8192; i=i+1)
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begin
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begin
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dut.ram_16x2k_pmem.ram_inst.mem[i] = pmem[i];
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dut.ram_16x8k_dp_pmem_shared.ram_dp_inst.mem[i] = pmem[i];
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end
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end
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end
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end
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//
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//
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// Generate Clock & Reset
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// Generate Clock & Reset
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| Line 332... |
Line 341... |
);
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);
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// Debug utility signals
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// Debug utility signals
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//----------------------------------------
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//----------------------------------------
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msp_debug msp_debug_0 (
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msp_debug msp_debug_omsp0 (
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// OUTPUTs
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// OUTPUTs
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.e_state (e_state), // Execution state
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.e_state (omsp0_e_state), // Execution state
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.i_state (i_state), // Instruction fetch state
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.i_state (omsp0_i_state), // Instruction fetch state
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.inst_cycle (inst_cycle), // Cycle number within current instruction
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.inst_cycle (omsp0_inst_cycle), // Cycle number within current instruction
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.inst_full (inst_full), // Currently executed instruction (full version)
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.inst_full (omsp0_inst_full), // Currently executed instruction (full version)
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.inst_number (inst_number), // Instruction number since last system reset
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.inst_number (omsp0_inst_number), // Instruction number since last system reset
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.inst_pc (inst_pc), // Instruction Program counter
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.inst_pc (omsp0_inst_pc), // Instruction Program counter
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.inst_short (inst_short), // Currently executed instruction (short version)
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.inst_short (omsp0_inst_short), // Currently executed instruction (short version)
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// INPUTs
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// INPUTs
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.mclk (mclk), // Main system clock
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.core_select (0) // Core selection
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.puc_rst (puc_rst) // Main system reset
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);
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msp_debug msp_debug_omsp1 (
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// OUTPUTs
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.e_state (omsp1_e_state), // Execution state
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.i_state (omsp1_i_state), // Instruction fetch state
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.inst_cycle (omsp1_inst_cycle), // Cycle number within current instruction
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.inst_full (omsp1_inst_full), // Currently executed instruction (full version)
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.inst_number (omsp1_inst_number), // Instruction number since last system reset
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.inst_pc (omsp1_inst_pc), // Instruction Program counter
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.inst_short (omsp1_inst_short), // Currently executed instruction (short version)
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// INPUTs
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.core_select (1) // Core selection
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);
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);
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//
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//
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// Generate Waveform
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// Generate Waveform
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//----------------------------------------
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//----------------------------------------
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| Line 383... |
Line 406... |
$finish;
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$finish;
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end
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end
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initial // Normal end of test
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initial // Normal end of test
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begin
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begin
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@(inst_pc===16'hffff)
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@(omsp0_inst_pc===16'hffff)
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$display(" ===============================================");
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$display(" ===============================================");
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if (error!=0)
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if (error!=0)
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begin
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begin
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$display("| SIMULATION FAILED |");
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$display("| SIMULATION FAILED |");
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$display("| (some verilog stimulus checks failed) |");
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$display("| (some verilog stimulus checks failed) |");
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