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Welcome to Xilinx CORE Generator.
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Welcome to Xilinx CORE Generator.
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Help system initialized.
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Help system initialized.
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The IP Catalog has been reloaded.
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The IP Catalog has been reloaded.
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Wrote CGP file for project 'coregen'.
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Opening project file
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Customize and GenerateINFO:sim:172 - Generating IP...
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/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
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Applying current project options...
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log/coregen/coregen.cgp.
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Finished applying current project options.
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Recustomize and Generate (Under Original Project Settings)INFO:sim:172 - Generating IP...
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Resolving generics for 'ram_16x512'...
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Resolving generics for 'ram_16x8k_dp'...
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Applying external generics to 'ram_16x512'...
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Applying external generics to 'ram_16x8k_dp'...
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Delivering associated files for 'ram_16x512'...
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Delivering associated files for 'ram_16x8k_dp'...
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WARNING:sim - Component blk_mem_gen_v7_2 does not have a valid model name for
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VHDL synthesis
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Delivering EJava files for 'ram_16x512'...
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Generating implementation netlist for 'ram_16x512'...
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INFO:sim - Pre-processing HDL files for 'ram_16x512'...
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Running synthesis for 'ram_16x512'
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Running ngcbuild...
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Writing VHO instantiation template for 'ram_16x512'...
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Writing VHDL instantiation wrapper for 'ram_16x512'...
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Writing VHDL behavioral simulation model for 'ram_16x512'...
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WARNING:sim - No files were found for the view xilinx_documentation
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Generating ASY schematic symbol...
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INFO:sim:949 - Finished generation of ASY schematic symbol.
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Generating metadata file...
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Generating ISE project file for 'ram_16x512'...
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Generating ISE project...
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XCO file found: ram_16x512.xco
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XMDF file found: ram_16x512_xmdf.tcl
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen/tmp/_cg/ram_16x512.asy -view all -origin_type imported
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen/tmp/_cg/ram_16x512.ngc -view all -origin_type created
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Checking file
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ve
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rilog/coregen/tmp/_cg/ram_16x512.ngc" for project device match ...
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File
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ve
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rilog/coregen/tmp/_cg/ram_16x512.ngc" device information matches project device.
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen/tmp/_cg/ram_16x512.vhd -view all -origin_type created
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INFO:HDLCompiler:1061 - Parsing VHDL file
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl
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/verilog/coregen/tmp/_cg/ram_16x512.vhd" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen/tmp/_cg/ram_16x512.vho -view all -origin_type imported
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen/tmp/_cg/ram_16x512_synth.vhd -view all -origin_type created
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INFO:HDLCompiler:1061 - Parsing VHDL file
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl
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/verilog/coregen/tmp/_cg/ram_16x512_synth.vhd" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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WARNING:ProjectMgmt - Duplicate Design Unit 'ram_16x512' found in library 'work'
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WARNING:ProjectMgmt -
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl
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/verilog/coregen/tmp/_cg/ram_16x512.vhd" line 43 (active)
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WARNING:ProjectMgmt -
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl
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/verilog/coregen/tmp/_cg/ram_16x512_synth.vhd" line 64
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INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
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Please set the new top explicitly by running the "project set top" command.
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To re-calculate the new top automatically, set the "Auto Implementation Top"
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property to true.
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Top level has been set to "/ram_16x512"
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Generating README file...
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Generating FLIST file...
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INFO:sim:948 - Finished FLIST file generation.
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Launching README viewer...
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Moving files to output directory...
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Finished moving files to output directory
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Saved CGP file for project 'coregen'.
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Saved CGP file for project 'coregen'.
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Regenerate (Under Current Project Settings)INFO:sim:172 - Generating IP...
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Applying current project options...
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Finished applying current project options.
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Resolving generics for 'ram_16x512'...
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WARNING:sim - A core named 'ram_16x512' already exists in the project. Output
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products for this core may be overwritten.
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Applying external generics to 'ram_16x512'...
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Delivering associated files for 'ram_16x512'...
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WARNING:sim - Component blk_mem_gen_v7_2 does not have a valid model name for
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Verilog synthesis
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Delivering EJava files for 'ram_16x512'...
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Generating implementation netlist for 'ram_16x512'...
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INFO:sim - Pre-processing HDL files for 'ram_16x512'...
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Running synthesis for 'ram_16x512'
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Running ngcbuild...
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Writing VEO instantiation template for 'ram_16x512'...
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Writing Verilog instantiation wrapper for 'ram_16x512'...
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Writing Verilog behavioral simulation model for 'ram_16x512'...
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WARNING:sim - No files were found for the view xilinx_documentation
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Generating ASY schematic symbol...
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INFO:sim:949 - Finished generation of ASY schematic symbol.
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Generating metadata file...
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Regenerating ISE project file for 'ram_16x512'...
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Generating ISE project...
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XCO file found: ram_16x512.xco
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XMDF file found: ram_16x512_xmdf.tcl
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen/tmp/_cg/ram_16x512.asy -view all -origin_type imported
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen/tmp/_cg/ram_16x512.ngc -view all -origin_type created
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Checking file
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ve
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rilog/coregen/tmp/_cg/ram_16x512.ngc" for project device match ...
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File
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ve
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rilog/coregen/tmp/_cg/ram_16x512.ngc" device information matches project device.
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen/tmp/_cg/ram_16x512.v -view all -origin_type created
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl
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/verilog/coregen/tmp/_cg/ram_16x512.v" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen/tmp/_cg/ram_16x512.veo -view all -origin_type imported
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen/tmp/_cg/ram_16x512_synth.v -view all -origin_type created
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl
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/verilog/coregen/tmp/_cg/ram_16x512_synth.v" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
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Please set the new top explicitly by running the "project set top" command.
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To re-calculate the new top automatically, set the "Auto Implementation Top"
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property to true.
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Top level has been set to "/ram_16x512"
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Generating README file...
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Generating FLIST file...
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INFO:sim:948 - Finished FLIST file generation.
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Moving files to output directory...
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Finished moving files to output directory
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Saved CGP file for project 'coregen'.
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Customize and GenerateINFO:sim:172 - Generating IP...
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Applying current project options...
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Finished applying current project options.
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Resolving generics for 'ram_16x2k'...
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Applying external generics to 'ram_16x2k'...
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Delivering associated files for 'ram_16x2k'...
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WARNING:sim - Component blk_mem_gen_v7_2 does not have a valid model name for
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WARNING:sim - Component blk_mem_gen_v7_2 does not have a valid model name for
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Verilog synthesis
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Verilog synthesis
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Delivering EJava files for 'ram_16x2k'...
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Delivering EJava files for 'ram_16x8k_dp'...
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Generating implementation netlist for 'ram_16x2k'...
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Generating implementation netlist for 'ram_16x8k_dp'...
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INFO:sim - Pre-processing HDL files for 'ram_16x2k'...
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INFO:sim - Pre-processing HDL files for 'ram_16x8k_dp'...
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Running synthesis for 'ram_16x2k'
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Running synthesis for 'ram_16x8k_dp'
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Running ngcbuild...
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Running ngcbuild...
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Writing VEO instantiation template for 'ram_16x2k'...
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Writing VEO instantiation template for 'ram_16x8k_dp'...
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Writing Verilog instantiation wrapper for 'ram_16x2k'...
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Writing Verilog instantiation wrapper for 'ram_16x8k_dp'...
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Writing Verilog behavioral simulation model for 'ram_16x2k'...
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Writing Verilog behavioral simulation model for 'ram_16x8k_dp'...
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WARNING:sim - No files were found for the view xilinx_documentation
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WARNING:sim - No files were found for the view xilinx_documentation
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Generating ASY schematic symbol...
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Generating ASY schematic symbol...
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INFO:sim:949 - Finished generation of ASY schematic symbol.
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INFO:sim:949 - Finished generation of ASY schematic symbol.
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Generating metadata file...
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Generating metadata file...
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Generating ISE project file for 'ram_16x2k'...
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Generating ISE project file for 'ram_16x8k_dp'...
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Generating ISE project...
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Generating ISE project...
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XCO file found: ram_16x2k.xco
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XCO file found: ram_16x8k_dp.xco
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XMDF file found: ram_16x2k_xmdf.tcl
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XMDF file found: ram_16x8k_dp_xmdf.tcl
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Adding
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
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ilog/coregen/tmp/_cg/ram_16x2k.asy -view all -origin_type imported
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log/coregen/tmp/_cg/ram_16x8k_dp.asy -view all -origin_type imported
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Adding
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
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ilog/coregen/tmp/_cg/ram_16x2k.ngc -view all -origin_type created
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log/coregen/tmp/_cg/ram_16x8k_dp.ngc -view all -origin_type created
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Checking file
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Checking file
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ve
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"/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/ver
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rilog/coregen/tmp/_cg/ram_16x2k.ngc" for project device match ...
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ilog/coregen/tmp/_cg/ram_16x8k_dp.ngc" for project device match ...
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File
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File
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ve
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"/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/ver
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rilog/coregen/tmp/_cg/ram_16x2k.ngc" device information matches project device.
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ilog/coregen/tmp/_cg/ram_16x8k_dp.ngc" device information matches project
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device.
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Adding
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
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ilog/coregen/tmp/_cg/ram_16x2k.v -view all -origin_type created
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log/coregen/tmp/_cg/ram_16x8k_dp.v -view all -origin_type created
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl
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"/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/
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/verilog/coregen/tmp/_cg/ram_16x2k.v" into library work
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verilog/coregen/tmp/_cg/ram_16x8k_dp.v" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
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ilog/coregen/tmp/_cg/ram_16x2k.veo -view all -origin_type imported
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log/coregen/tmp/_cg/ram_16x8k_dp.veo -view all -origin_type imported
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Adding
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
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ilog/coregen/tmp/_cg/ram_16x2k_synth.v -view all -origin_type created
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log/coregen/tmp/_cg/ram_16x8k_dp_synth.v -view all -origin_type created
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl
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"/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/
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/verilog/coregen/tmp/_cg/ram_16x2k_synth.v" into library work
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verilog/coregen/tmp/_cg/ram_16x8k_dp_synth.v" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
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INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
|
Please set the new top explicitly by running the "project set top" command.
|
Please set the new top explicitly by running the "project set top" command.
|
To re-calculate the new top automatically, set the "Auto Implementation Top"
|
To re-calculate the new top automatically, set the "Auto Implementation Top"
|
property to true.
|
property to true.
|
Top level has been set to "/ram_16x2k"
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Top level has been set to "/ram_16x8k_dp"
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Generating README file...
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Generating README file...
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Generating FLIST file...
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Generating FLIST file...
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INFO:sim:948 - Finished FLIST file generation.
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INFO:sim:948 - Finished FLIST file generation.
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Launching README viewer...
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Launching README viewer...
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Moving files to output directory...
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Moving files to output directory...
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Finished moving files to output directory
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Finished moving files to output directory
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Saved CGP file for project 'coregen'.
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Saved CGP file for project 'coregen'.
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Saved CGP file for project 'coregen'.
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Closed project file.
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Closed project file.
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