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// along with this source; if not, write to the Free Software Foundation,
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: openMSP430_fpga.v
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// *File Name: omsp_system_1.v
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//
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//
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// *Module Description:
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// *Module Description:
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// openMSP430 FPGA Top-level for the Avnet LX9 Microboard
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// openMSP430 System 0.
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// This core is dedicated to communication and
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// display (i.e. UART, LEDs and 7-segment modport)
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// It can also read the switches value.
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//
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//
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// *Author(s):
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// *Author(s):
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// - Ricardo Ribalda, ricardo.ribalda@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "openmsp430/openMSP430_defines.v"
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`include "openmsp430/openMSP430_defines.v"
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// Clock & Reset
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// Clock & Reset
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dco_clk, // Fast oscillator (fast clock)
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dco_clk, // Fast oscillator (fast clock)
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reset_n, // Reset Pin (low active, asynchronous and non-glitchy)
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reset_n, // Reset Pin (low active, asynchronous and non-glitchy)
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// Serial Debug Interface (UART)
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dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
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dbg_uart_txd, // Debug interface: UART TXD
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// Serial Debug Interface (I2C)
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// Serial Debug Interface (I2C)
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dbg_i2c_addr, // Debug interface: I2C Address
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dbg_i2c_addr, // Debug interface: I2C Address
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dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
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dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
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dbg_i2c_scl, // Debug interface: I2C SCL
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dbg_i2c_scl, // Debug interface: I2C SCL
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dbg_i2c_sda_in, // Debug interface: I2C SDA IN
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dbg_i2c_sda_in, // Debug interface: I2C SDA IN
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// Clock & Reset
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// Clock & Reset
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input dco_clk; // Fast oscillator (fast clock)
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input dco_clk; // Fast oscillator (fast clock)
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input reset_n; // Reset Pin (low active, asynchronous and non-glitchy)
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input reset_n; // Reset Pin (low active, asynchronous and non-glitchy)
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// Serial Debug Interface (UART)
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input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
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output dbg_uart_txd; // Debug interface: UART TXD
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// Serial Debug Interface (I2C)
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// Serial Debug Interface (I2C)
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input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
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input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
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input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
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input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
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input dbg_i2c_scl; // Debug interface: I2C SCL
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input dbg_i2c_scl; // Debug interface: I2C SCL
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input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
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input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
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input uart_rxd; // UART Data Receive (RXD)
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input uart_rxd; // UART Data Receive (RXD)
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output uart_txd; // UART Data Transmit (TXD)
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output uart_txd; // UART Data Transmit (TXD)
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// Switches & LEDs
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// Switches & LEDs
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input [3:0] switch; // Input switches
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input [3:0] switch; // Input switches
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output [3:0] led; // LEDs
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output [1:0] led; // LEDs
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//=============================================================================
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//=============================================================================
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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//=============================================================================
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//=============================================================================
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wire smclk_en;
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wire smclk_en;
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wire puc_rst;
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wire puc_rst;
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// Debug interface
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// Debug interface
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wire dbg_freeze;
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wire dbg_freeze;
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wire dbg_uart_txd;
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wire dbg_uart_rxd;
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// Data memory
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// Data memory
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wire [`DMEM_MSB:0] dmem_addr;
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wire [`DMEM_MSB:0] dmem_addr;
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wire dmem_cen;
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wire dmem_cen;
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wire [15:0] dmem_din;
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wire [15:0] dmem_din;
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//=============================================================================
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//=============================================================================
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// 2) OPENMSP430 CORE
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// 2) OPENMSP430 CORE
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//=============================================================================
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//=============================================================================
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openMSP430 #(.INST_NR (0),
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openMSP430 #(.INST_NR (0),
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.TOTAL_NR(0)) openMSP430_0 (
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.TOTAL_NR(1)) openMSP430_0 (
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// OUTPUTs
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// OUTPUTs
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.aclk (), // ASIC ONLY: ACLK
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.aclk (), // ASIC ONLY: ACLK
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.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
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.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
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.dbg_freeze (dbg_freeze), // Freeze peripherals
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.dbg_freeze (dbg_freeze), // Freeze peripherals
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.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
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.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
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.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
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.dbg_uart_txd (), // Debug interface: UART TXD
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.dco_enable (), // ASIC ONLY: Fast oscillator enable
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.dco_enable (), // ASIC ONLY: Fast oscillator enable
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.dco_wkup (), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
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.dco_wkup (), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
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.dmem_addr (dmem_addr), // Data Memory address
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.dmem_addr (dmem_addr), // Data Memory address
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.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
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.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
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.dmem_din (dmem_din), // Data Memory data input
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.dmem_din (dmem_din), // Data Memory data input
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.dbg_en (1'b1), // Debug interface enable (asynchronous and non-glitchy)
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.dbg_en (1'b1), // Debug interface enable (asynchronous and non-glitchy)
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.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
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.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
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.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
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.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
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.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
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.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
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.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
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.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
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.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
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.dbg_uart_rxd (1'b1), // Debug interface: UART RXD (asynchronous)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dmem_dout (dmem_dout), // Data Memory data output
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.dmem_dout (dmem_dout), // Data Memory data output
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.irq (irq_bus), // Maskable interrupts
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.irq (irq_bus), // Maskable interrupts
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.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)
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.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)
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.nmi (nmi), // Non-maskable interrupt (asynchronous)
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.nmi (nmi), // Non-maskable interrupt (asynchronous)
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.per_we (per_we), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc_rst (puc_rst) // Main system reset
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.puc_rst (puc_rst) // Main system reset
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);
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);
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// Assign LEDs
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// Assign LEDs
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assign led = p2_dout[3:0] & p2_dout_en[3:0];
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assign led = p2_dout[1:0] & p2_dout_en[1:0];
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// Assign Switches
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// Assign Switches
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assign p1_din[7:4] = 4'h0;
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assign p1_din[7:4] = 4'h0;
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assign p1_din[3:0] = switch;
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assign p1_din[3:0] = switch;
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1'b0, // Vector 10 (0xFFF4) - Watchdog -
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1'b0, // Vector 10 (0xFFF4) - Watchdog -
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irq_ta0, // Vector 9 (0xFFF2)
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irq_ta0, // Vector 9 (0xFFF2)
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irq_ta1, // Vector 8 (0xFFF0)
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irq_ta1, // Vector 8 (0xFFF0)
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irq_uart_rx, // Vector 7 (0xFFEE)
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irq_uart_rx, // Vector 7 (0xFFEE)
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irq_uart_tx, // Vector 6 (0xFFEC)
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irq_uart_tx, // Vector 6 (0xFFEC)
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1'b0, // Vector 5 (0xFFEA)
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1'b0, // Vector 5 (0xFFEA) - Reserved (Timer-A 0 from system 1)
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1'b0, // Vector 4 (0xFFE8)
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1'b0, // Vector 4 (0xFFE8) - Reserved (Timer-A 1 from system 1)
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irq_port2, // Vector 3 (0xFFE6)
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irq_port2, // Vector 3 (0xFFE6)
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irq_port1, // Vector 2 (0xFFE4)
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irq_port1, // Vector 2 (0xFFE4)
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1'b0, // Vector 1 (0xFFE2)
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1'b0, // Vector 1 (0xFFE2) - Reserved (Port 2 from system 1)
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1'b0}; // Vector 0 (0xFFE0)
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1'b0}; // Vector 0 (0xFFE0) - Reserved (Port 1 from system 1)
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endmodule // omsp_system_0
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endmodule // omsp_system_0
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