URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [omsp_uart.v] - Diff between revs 157 and 197

Rev 157	Rev 197
Line 229...	Line 229...
`wire baud_hi_wr = BAUD_HI[0] ? reg_hi_wr[BAUD_HI] : reg_lo_wr[BAUD_HI];`	`wire baud_hi_wr = BAUD_HI[0] ? reg_hi_wr[BAUD_HI] : reg_lo_wr[BAUD_HI];`
`wire [7:0] baud_hi_nxt = BAUD_HI[0] ? per_din[15:8] : per_din[7:0];`	`wire [7:0] baud_hi_nxt = BAUD_HI[0] ? per_din[15:8] : per_din[7:0];`

`always @ (posedge mclk or posedge puc_rst)`	`always @ (posedge mclk or posedge puc_rst)`
`if (puc_rst) baud_hi <= 8'h00;`	`if (puc_rst) baud_hi <= 8'h00;`
`else if (baud_lo_wr) baud_hi <= baud_hi_nxt;`	`else if (baud_hi_wr) baud_hi <= baud_hi_nxt;`


`wire [15:0] baudrate = {baud_hi, baud_lo};`	`wire [15:0] baudrate = {baud_hi, baud_lo};`


Line 295...	Line 295...
`//--------------------------------`	`//--------------------------------`
`wire uart_rxd_sync_n;`	`wire uart_rxd_sync_n;`

`omsp_sync_cell sync_cell_uart_rxd (`	`omsp_sync_cell sync_cell_uart_rxd (`
`.data_out (uart_rxd_sync_n),`	`.data_out (uart_rxd_sync_n),`
	`.data_meta (),`
`.data_in (~uart_rxd),`	`.data_in (~uart_rxd),`
`.clk (mclk),`	`.clk (mclk),`
`.rst (puc_rst)`	`.rst (puc_rst)`
`);`	`);`
`wire uart_rxd_sync = ~uart_rxd_sync_n;`	`wire uart_rxd_sync = ~uart_rxd_sync_n;`