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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [openMSP430_fpga.v] - Diff between revs 167 and 212

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Rev 167	Rev 212
Line 476...	Line 476...
`DCM_SP #(.CLKFX_MULTIPLY(7),`	`DCM_SP #(.CLKFX_MULTIPLY(7),`
`.CLKFX_DIVIDE(10),`	`.CLKFX_DIVIDE(10),`
`.CLKIN_PERIOD(25.000)) dcm_inst (`	`.CLKIN_PERIOD(25.000)) dcm_inst (`

`// OUTPUTs`	`// OUTPUTs`
	`.CLKDV (),`
`.CLKFX (dcm_clkfx),`	`.CLKFX (dcm_clkfx),`
`.CLK0 (dcm_clk0),`	`.CLKFX180 (),`
`.LOCKED (dcm_locked),`	`.LOCKED (dcm_locked),`
	`.PSDONE (),`

	`.STATUS (),`

	`.CLK0 (dcm_clk0),`
	`.CLK180 (),`
	`.CLK270 (),`
	`.CLK2X (),`
	`.CLK2X180 (),`
	`.CLK90 (),`

`// INPUTs`	`// INPUTs`
`.CLKFB (dcm_clkfb),`	`.CLKFB (dcm_clkfb),`
`.CLKIN (clk_40mhz),`	`.CLKIN (clk_40mhz),`
	`.DSSEN (1'b0),`

	`.PSCLK (1'b0),`
`.PSEN (1'b0),`	`.PSEN (1'b0),`
	`.PSINCDEC (1'b0),`
`.RST (reset_pin)`	`.RST (reset_pin)`
`);`	`);`

`BUFG CLK0_BUFG_INST (`	`BUFG CLK0_BUFG_INST (`
`.I(dcm_clk0),`	`.I(dcm_clk0),`
Line 850...	Line 865...
`assign chipscope_trigger[23:3] = 21'h00_0000;`	`assign chipscope_trigger[23:3] = 21'h00_0000;`
`endif	`endif

`endmodule // openMSP430_fpga`	`endmodule // openMSP430_fpga`


`No newline at end of file`	`No newline at end of file`

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