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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [openmsp430/] [omsp_watchdog.v] - Diff between revs 157 and 181

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Rev 157 Rev 181
Line 174... Line 174...
parameter [7:0] WDTNMIES_MASK = 8'h40;
parameter [7:0] WDTNMIES_MASK = 8'h40;
`else
`else
parameter [7:0] WDTNMIES_MASK = 8'h00;
parameter [7:0] WDTNMIES_MASK = 8'h00;
`endif
`endif
 
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
  `ifdef WATCHDOG_MUX
  `ifdef WATCHDOG_MUX
parameter [7:0] WDTSSEL_MASK  = 8'h04;
parameter [7:0] WDTSSEL_MASK  = 8'h04;
  `else
  `else
parameter [7:0] WDTSSEL_MASK  = 8'h00;
parameter [7:0] WDTSSEL_MASK  = 8'h00;
  `endif
  `endif
Line 227... Line 227...
 
 
 
 
//=============================================================================
//=============================================================================
// 5)  WATCHDOG TIMER (ASIC IMPLEMENTATION)
// 5)  WATCHDOG TIMER (ASIC IMPLEMENTATION)
//=============================================================================
//=============================================================================
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
 
// Watchdog clock source selection
// Watchdog clock source selection
//---------------------------------
//---------------------------------
wire wdt_clk;
wire wdt_clk;
 
 

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