| Line 39... |
Line 39... |
|
|
+incdir+../../../bench/verilog/
|
+incdir+../../../bench/verilog/
|
../../../bench/verilog/tb_openMSP430_fpga.v
|
../../../bench/verilog/tb_openMSP430_fpga.v
|
../../../bench/verilog/msp_debug.v
|
../../../bench/verilog/msp_debug.v
|
../../../bench/verilog/glbl.v
|
../../../bench/verilog/glbl.v
|
../../../bench/verilog/ram_16x512.v
|
../../../bench/verilog/ram_16x8k_dp.v
|
../../../bench/verilog/ram_16x2k.v
|
../../../bench/verilog/ram_16x1k_dp.v
|
../../../bench/verilog/ram.v
|
../../../bench/verilog/ram_dp.v
|
|
../../../bench/verilog/ram_16x1k_sp.v
|
|
../../../bench/verilog/ram_sp.v
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// Xilinx library
|
// Xilinx library
|
//=============================================================================
|
//=============================================================================
|
| Line 61... |
Line 63... |
//=============================================================================
|
//=============================================================================
|
|
|
+incdir+../../../rtl/verilog/
|
+incdir+../../../rtl/verilog/
|
../../../rtl/verilog/openMSP430_fpga.v
|
../../../rtl/verilog/openMSP430_fpga.v
|
../../../rtl/verilog/omsp_system_0.v
|
../../../rtl/verilog/omsp_system_0.v
|
|
../../../rtl/verilog/omsp_system_1.v
|
../../../rtl/verilog/io_mux.v
|
../../../rtl/verilog/io_mux.v
|
../../../rtl/verilog/omsp_uart.v
|
../../../rtl/verilog/omsp_uart.v
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
