URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 167 |
Rev 202 |
| Line 51... |
Line 51... |
//=============================================================================
|
//=============================================================================
|
// Xilinx library
|
// Xilinx library
|
//=============================================================================
|
//=============================================================================
|
+libext+.v
|
+libext+.v
|
|
|
-y /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/
|
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/
|
-y /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/
|
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/simprims/
|
-y /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/
|
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/XilinxCoreLib/
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// FPGA Specific modules
|
// FPGA Specific modules
|
//=============================================================================
|
//=============================================================================
|
| Line 98... |
Line 98... |
../../../rtl/verilog/openmsp430/omsp_clock_gate.v
|
../../../rtl/verilog/openmsp430/omsp_clock_gate.v
|
../../../rtl/verilog/openmsp430/omsp_clock_mux.v
|
../../../rtl/verilog/openmsp430/omsp_clock_mux.v
|
../../../rtl/verilog/openmsp430/periph/omsp_gpio.v
|
../../../rtl/verilog/openmsp430/periph/omsp_gpio.v
|
../../../rtl/verilog/openmsp430/periph/omsp_timerA.v
|
../../../rtl/verilog/openmsp430/periph/omsp_timerA.v
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.