URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [sim/] [rtl_sim/] [src/] [submit.prj] - Diff between revs 157 and 162

Rev 157	Rev 162
Line 27...	Line 27...
`verilog work ../../../rtl/verilog/openmsp430/omsp_mem_backbone.v`	`verilog work ../../../rtl/verilog/openmsp430/omsp_mem_backbone.v`
`verilog work ../../../rtl/verilog/openmsp430/omsp_clock_module.v`	`verilog work ../../../rtl/verilog/openmsp430/omsp_clock_module.v`
`verilog work ../../../rtl/verilog/openmsp430/omsp_dbg.v`	`verilog work ../../../rtl/verilog/openmsp430/omsp_dbg.v`
`verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v`	`verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v`
`verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_uart.v`	`verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_uart.v`
	`verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_i2c.v`
`verilog work ../../../rtl/verilog/openmsp430/omsp_watchdog.v`	`verilog work ../../../rtl/verilog/openmsp430/omsp_watchdog.v`
`verilog work ../../../rtl/verilog/openmsp430/omsp_multiplier.v`	`verilog work ../../../rtl/verilog/openmsp430/omsp_multiplier.v`
`verilog work ../../../rtl/verilog/openmsp430/omsp_sync_reset.v`	`verilog work ../../../rtl/verilog/openmsp430/omsp_sync_reset.v`
`verilog work ../../../rtl/verilog/openmsp430/omsp_sync_cell.v`	`verilog work ../../../rtl/verilog/openmsp430/omsp_sync_cell.v`
`verilog work ../../../rtl/verilog/openmsp430/omsp_scan_mux.v`	`verilog work ../../../rtl/verilog/openmsp430/omsp_scan_mux.v`