URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [sim/] [rtl_sim/] [src/] [submit.prj] - Diff between revs 162 and 167

Go to most recent revision | Show entire file | Details | Blame | View Log

Browse

Tools

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [sim/] [rtl_sim/] [src/] [submit.prj] - Diff between revs 162 and 167

Rev 162	Rev 167
Line 1...	Line 1...

`verilog work ../../../bench/verilog/tb_openMSP430_fpga.v`	`verilog work ../../../bench/verilog/tb_openMSP430_fpga.v`
`verilog work ../../../bench/verilog/msp_debug.v`	`verilog work ../../../bench/verilog/msp_debug.v`
`verilog work ../../../bench/verilog/glbl.v`	`verilog work ../../../bench/verilog/glbl.v`
`verilog work ../../../bench/verilog/ram_16x512.v`	`verilog work ../../../bench/verilog/ram_16x8k_dp.v`
`verilog work ../../../bench/verilog/ram_16x2k.v`	`verilog work ../../../bench/verilog/ram_16x1k_dp.v`
`verilog work ../../../bench/verilog/ram.v`	`verilog work ../../../bench/verilog/ram_dp.v`
	`verilog work ../../../bench/verilog/ram_16x1k_sp.v`
	`verilog work ../../../bench/verilog/ram_sp.v`

`verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/DCM_SP.v`	`verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/DCM_SP.v`
`verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IBUF.v`	`verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IBUF.v`
`verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IBUFG.v`	`verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IBUFG.v`
`verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/BUFG.v`	`verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/BUFG.v`
`verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/OBUF.v`	`verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/OBUF.v`
`verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IOBUF.v`	`verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IOBUF.v`

`verilog work ../../../rtl/verilog/openMSP430_fpga.v`	`verilog work ../../../rtl/verilog/openMSP430_fpga.v`
`verilog work ../../../rtl/verilog/omsp_system_0.v`	`verilog work ../../../rtl/verilog/omsp_system_0.v`
	`verilog work ../../../rtl/verilog/omsp_system_1.v`
`verilog work ../../../rtl/verilog/io_mux.v`	`verilog work ../../../rtl/verilog/io_mux.v`
`verilog work ../../../rtl/verilog/omsp_uart.v`	`verilog work ../../../rtl/verilog/omsp_uart.v`

`verilog work ../../../rtl/verilog/openmsp430/openMSP430.v`	`verilog work ../../../rtl/verilog/openmsp430/openMSP430.v`
`verilog work ../../../rtl/verilog/openmsp430/omsp_frontend.v`	`verilog work ../../../rtl/verilog/openmsp430/omsp_frontend.v`