URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [synthesis/] [xilinx/] [0_create_bitstream.sh] - Diff between revs 157 and 167

Rev 157	Rev 167
Line 9...	Line 9...
`rm -rf ./WORK`	`rm -rf ./WORK`
`mkdir WORK`	`mkdir WORK`
`cd ./WORK`	`cd ./WORK`

`# Create links for RAM & ROM ngc files`	`# Create links for RAM & ROM ngc files`
`ln -s ../../../rtl/verilog/coregen/ram_16x512.ngc .`	`ln -s ../../../rtl/verilog/coregen/ram_16x1k_sp.ngc .`
`ln -s ../../../rtl/verilog/coregen/ram_16x2k.ngc .`	`ln -s ../../../rtl/verilog/coregen/ram_16x1k_dp.ngc .`
	`ln -s ../../../rtl/verilog/coregen/ram_16x8k_dp.ngc .`

`# Create links for Chipscope ngc files`	`# Create links for Chipscope ngc files`
`ln -s ../../../rtl/verilog/coregen_chipscope/chipscope_icon.ngc .`	`ln -s ../../../rtl/verilog/coregen_chipscope/chipscope_icon.ngc .`
`ln -s ../../../rtl/verilog/coregen_chipscope/chipscope_ila.ngc .`	`ln -s ../../../rtl/verilog/coregen_chipscope/chipscope_ila.ngc .`