URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [registers.v] - Diff between revs 37 and 111

Rev 37	Rev 111
Line 29...	Line 29...
`//`	`//`
`// *Author(s):`	`// *Author(s):`
`// - Olivier Girard, olgirard@gmail.com`	`// - Olivier Girard, olgirard@gmail.com`
`//`	`//`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`// $Rev: 37 $`	`// $Rev: 111 $`
`// $LastChangedBy: olivier.girard $`	`// $LastChangedBy: olivier.girard $`
`// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $`	`// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`

`// CPU registers`	`// CPU registers`
`//======================`	`//======================`

Line 152...	Line 152...

`// CPU internals`	`// CPU internals`
`//======================`	`//======================`

`wire mclk = dut.openMSP430_0.mclk;`	`wire mclk = dut.openMSP430_0.mclk;`
`wire puc = dut.openMSP430_0.puc;`	`wire puc_rst = dut.openMSP430_0.puc_rst;`

`No newline at end of file`	`No newline at end of file`