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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [registers.v] - Diff between revs 136 and 143

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Rev 136	Rev 143
Line 30...	Line 30...
`//`	`//`
`// *Author(s):`	`// *Author(s):`
`// - Olivier Girard, olgirard@gmail.com`	`// - Olivier Girard, olgirard@gmail.com`
`//`	`//`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`// $Rev: 136 $`	`// $Rev: 143 $`
`// $LastChangedBy: olivier.girard $`	`// $LastChangedBy: olivier.girard $`
`// $LastChangedDate: 2012-03-22 22:14:16 +0100 (Thu, 22 Mar 2012) $`	`// $LastChangedDate: 2012-05-09 22:20:03 +0200 (Wed, 09 May 2012) $`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`

`// CPU registers`	`// CPU registers`
`//======================`	`//======================`

Line 128...	Line 128...
`wire [15:0] mem280 = {dut.ram_8x512_hi_0.inst.mem[64], dut.ram_8x512_lo_0.inst.mem[64]};`	`wire [15:0] mem280 = {dut.ram_8x512_hi_0.inst.mem[64], dut.ram_8x512_lo_0.inst.mem[64]};`


`// Program Memory cells`	`// Program Memory cells`
`//======================`	`//======================`
`reg [15:0] pmem [2047:0];`	`reg [15:0] pmem [0:2047];`

`// Interrupt vectors`	`// Interrupt vectors`
wire [15:0] irq_vect_15 = pmem[(1<<(`PMEM_MSB+1))-1]; // RESET Vector	wire [15:0] irq_vect_15 = pmem[(1<<(`PMEM_MSB+1))-1]; // RESET Vector
wire [15:0] irq_vect_14 = pmem[(1<<(`PMEM_MSB+1))-2]; // NMI	wire [15:0] irq_vect_14 = pmem[(1<<(`PMEM_MSB+1))-2]; // NMI
wire [15:0] irq_vect_13 = pmem[(1<<(`PMEM_MSB+1))-3]; // IRQ 13	wire [15:0] irq_vect_13 = pmem[(1<<(`PMEM_MSB+1))-3]; // IRQ 13

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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [registers.v] - Diff between revs 136 and 143