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Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 16 $
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// $Rev: 37 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-04 23:03:47 +0200 (Tue, 04 Aug 2009) $
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// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// CPU registers
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// CPU registers
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//======================
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//======================
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wire [15:0] r13 = dut.openMSP430_0.execution_unit_0.register_file_0.r13;
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wire [15:0] r13 = dut.openMSP430_0.execution_unit_0.register_file_0.r13;
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wire [15:0] r14 = dut.openMSP430_0.execution_unit_0.register_file_0.r14;
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wire [15:0] r14 = dut.openMSP430_0.execution_unit_0.register_file_0.r14;
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wire [15:0] r15 = dut.openMSP430_0.execution_unit_0.register_file_0.r15;
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wire [15:0] r15 = dut.openMSP430_0.execution_unit_0.register_file_0.r15;
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// RAM cells
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// Data Memory cells
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//======================
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//======================
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wire [15:0] mem200 = {dut.ram_8x512_hi_0.inst.mem[0], dut.ram_8x512_lo_0.inst.mem[0]};
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wire [15:0] mem200 = {dut.ram_8x512_hi_0.inst.mem[0], dut.ram_8x512_lo_0.inst.mem[0]};
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wire [15:0] mem202 = {dut.ram_8x512_hi_0.inst.mem[1], dut.ram_8x512_lo_0.inst.mem[1]};
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wire [15:0] mem202 = {dut.ram_8x512_hi_0.inst.mem[1], dut.ram_8x512_lo_0.inst.mem[1]};
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wire [15:0] mem204 = {dut.ram_8x512_hi_0.inst.mem[2], dut.ram_8x512_lo_0.inst.mem[2]};
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wire [15:0] mem204 = {dut.ram_8x512_hi_0.inst.mem[2], dut.ram_8x512_lo_0.inst.mem[2]};
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wire [15:0] mem27C = {dut.ram_8x512_hi_0.inst.mem[62], dut.ram_8x512_lo_0.inst.mem[62]};
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wire [15:0] mem27C = {dut.ram_8x512_hi_0.inst.mem[62], dut.ram_8x512_lo_0.inst.mem[62]};
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wire [15:0] mem27E = {dut.ram_8x512_hi_0.inst.mem[63], dut.ram_8x512_lo_0.inst.mem[63]};
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wire [15:0] mem27E = {dut.ram_8x512_hi_0.inst.mem[63], dut.ram_8x512_lo_0.inst.mem[63]};
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wire [15:0] mem280 = {dut.ram_8x512_hi_0.inst.mem[64], dut.ram_8x512_lo_0.inst.mem[64]};
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wire [15:0] mem280 = {dut.ram_8x512_hi_0.inst.mem[64], dut.ram_8x512_lo_0.inst.mem[64]};
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// ROM cells
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// Program Memory cells
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//======================
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//======================
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reg [15:0] rom_mem [2047:0];
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reg [15:0] pmem [2047:0];
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// Interrupt vectors
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// Interrupt vectors
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wire [15:0] irq_vect_15 = rom_mem[(1<<(`ROM_MSB+1))-1]; // RESET Vector
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wire [15:0] irq_vect_15 = pmem[(1<<(`PMEM_MSB+1))-1]; // RESET Vector
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wire [15:0] irq_vect_14 = rom_mem[(1<<(`ROM_MSB+1))-2]; // NMI
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wire [15:0] irq_vect_14 = pmem[(1<<(`PMEM_MSB+1))-2]; // NMI
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wire [15:0] irq_vect_13 = rom_mem[(1<<(`ROM_MSB+1))-3]; // IRQ 13
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wire [15:0] irq_vect_13 = pmem[(1<<(`PMEM_MSB+1))-3]; // IRQ 13
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wire [15:0] irq_vect_12 = rom_mem[(1<<(`ROM_MSB+1))-4]; // IRQ 12
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wire [15:0] irq_vect_12 = pmem[(1<<(`PMEM_MSB+1))-4]; // IRQ 12
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wire [15:0] irq_vect_11 = rom_mem[(1<<(`ROM_MSB+1))-5]; // IRQ 11
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wire [15:0] irq_vect_11 = pmem[(1<<(`PMEM_MSB+1))-5]; // IRQ 11
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wire [15:0] irq_vect_10 = rom_mem[(1<<(`ROM_MSB+1))-6]; // IRQ 10
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wire [15:0] irq_vect_10 = pmem[(1<<(`PMEM_MSB+1))-6]; // IRQ 10
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wire [15:0] irq_vect_09 = rom_mem[(1<<(`ROM_MSB+1))-7]; // IRQ 9
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wire [15:0] irq_vect_09 = pmem[(1<<(`PMEM_MSB+1))-7]; // IRQ 9
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wire [15:0] irq_vect_08 = rom_mem[(1<<(`ROM_MSB+1))-8]; // IRQ 8
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wire [15:0] irq_vect_08 = pmem[(1<<(`PMEM_MSB+1))-8]; // IRQ 8
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wire [15:0] irq_vect_07 = rom_mem[(1<<(`ROM_MSB+1))-9]; // IRQ 7
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wire [15:0] irq_vect_07 = pmem[(1<<(`PMEM_MSB+1))-9]; // IRQ 7
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wire [15:0] irq_vect_06 = rom_mem[(1<<(`ROM_MSB+1))-10]; // IRQ 6
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wire [15:0] irq_vect_06 = pmem[(1<<(`PMEM_MSB+1))-10]; // IRQ 6
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wire [15:0] irq_vect_05 = rom_mem[(1<<(`ROM_MSB+1))-11]; // IRQ 5
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wire [15:0] irq_vect_05 = pmem[(1<<(`PMEM_MSB+1))-11]; // IRQ 5
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wire [15:0] irq_vect_04 = rom_mem[(1<<(`ROM_MSB+1))-12]; // IRQ 4
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wire [15:0] irq_vect_04 = pmem[(1<<(`PMEM_MSB+1))-12]; // IRQ 4
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wire [15:0] irq_vect_03 = rom_mem[(1<<(`ROM_MSB+1))-13]; // IRQ 3
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wire [15:0] irq_vect_03 = pmem[(1<<(`PMEM_MSB+1))-13]; // IRQ 3
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wire [15:0] irq_vect_02 = rom_mem[(1<<(`ROM_MSB+1))-14]; // IRQ 2
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wire [15:0] irq_vect_02 = pmem[(1<<(`PMEM_MSB+1))-14]; // IRQ 2
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wire [15:0] irq_vect_01 = rom_mem[(1<<(`ROM_MSB+1))-15]; // IRQ 1
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wire [15:0] irq_vect_01 = pmem[(1<<(`PMEM_MSB+1))-15]; // IRQ 1
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wire [15:0] irq_vect_00 = rom_mem[(1<<(`ROM_MSB+1))-16]; // IRQ 0
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wire [15:0] irq_vect_00 = pmem[(1<<(`PMEM_MSB+1))-16]; // IRQ 0
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// CPU internals
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// CPU internals
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//======================
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//======================
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