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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Diff between revs 111 and 153

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Rev 111 Rev 153
Line 29... Line 29...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 111 $
// $Rev: 153 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
// $LastChangedDate: 2012-08-22 00:27:18 +0200 (Wed, 22 Aug 2012) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`include "timescale.v"
`include "timescale.v"
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
Line 344... Line 344...
// End of simulation
// End of simulation
//----------------------------------------
//----------------------------------------
 
 
initial // Timeout
initial // Timeout
  begin
  begin
 
   `ifdef NO_TIMEOUT
 
   `else
 
     `ifdef VERY_LONG_TIMEOUT
 
       #500000000;
 
     `else
 
     `ifdef LONG_TIMEOUT
 
       #5000000;
 
     `else
     #500000;
     #500000;
 
     `endif
 
     `endif
     $display(" ===============================================");
     $display(" ===============================================");
     $display("|               SIMULATION FAILED               |");
     $display("|               SIMULATION FAILED               |");
     $display("|              (simulation Timeout)             |");
     $display("|              (simulation Timeout)             |");
     $display(" ===============================================");
     $display(" ===============================================");
     $finish;
     $finish;
 
   `endif
  end
  end
 
 
initial // Normal end of test
initial // Normal end of test
  begin
  begin
     @(inst_pc===16'hffff)
     @(inst_pc===16'hffff)

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