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Rev 37 |
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Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 23 $
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// $Rev: 37 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
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// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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module tb_openMSP430_fpga;
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module tb_openMSP430_fpga;
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Line 115... |
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// Verilog stimulus
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// Verilog stimulus
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`include "stimulus.v"
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`include "stimulus.v"
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//
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//
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// Initialize ROM
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// Initialize Program Memory
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//------------------------------
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//------------------------------
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initial
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initial
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begin
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begin
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// Read memory file
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// Read memory file
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$readmemh("./rom.mem", rom_mem);
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$readmemh("./pmem.mem", pmem);
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// Update Xilinx memory banks
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// Update Xilinx memory banks
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for (i=0; i<2048; i=i+1)
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for (i=0; i<2048; i=i+1)
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begin
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begin
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dut.rom_8x2k_hi_0.inst.mem[i] = rom_mem[i][15:8];
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dut.rom_8x2k_hi_0.inst.mem[i] = pmem[i][15:8];
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dut.rom_8x2k_lo_0.inst.mem[i] = rom_mem[i][7:0];
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dut.rom_8x2k_lo_0.inst.mem[i] = pmem[i][7:0];
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end
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end
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end
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end
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//
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//
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// Generate Clock & Reset
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// Generate Clock & Reset
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